Challenges in Using UVM at SoC Level


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Challenges in Using UVM at SoC Level

  1. 1. Challenges in using UVM at SoClevelRohit JindalST Microelectronics
  2. 2. 2Agenda General Overview of UVM Challenges in using UVM at SoC level Proposal for using UVM at SoC level
  3. 3. What is UVM?Universal Verification Methodology Testbenches for HDL designs UVM has SystemVerilog Base Class Library Based on constrained Random Verification approach Industry standard developed by Accellera Apache 2.0 open-source license Key features of the methodology: Data design and stimulus generation Building and running a verification environment 3C : Checker, Coverage and Constrains3
  4. 4. 4The Goal : AutomationSource: Accellera DAC Presentation
  5. 5. 5Key Features of UVM [1] Built-in automation Transaction manipulation (Print / Pack / [Deep] Copy / Record) Defined testbench build and hook-up mechanism Flexible automatic test phase interface Lot of phases defined for synchronization Powerful stimulus generation mechanism using sequences On-the-fly randomization control Sequence Layering & nested sequence Virtual sequences [Controlling multiple sequencers from ‘central place’] TLM communication Modular and Language independent Supports reuse Module-to-system Project-to-project
  6. 6. 6Key Features of UVM [2] Sequences or Testcases UVM Tests or sequences separated from TestBench environment Uniformity Standard structure for all Testbench components UVM factories UVM factories give flexibility Easy to update or modify components without changing original code Configuration UVM configuration helps in customizing the environment from Top or anywhere And more… Messaging utilities with on-the-fly control over verbosity Ensures random stability Compile once and run many times using snapshot
  7. 7. 77Env(UVC)AgentAgent7Reusable UVM Component ArchitectureAgentSequencersequencestlm i/fDriverviftlm i/fConfig:active_passive• Generates sequences oftransactionsand passes them to the driver• Connected to the driver viaTLM interface• Pulls items from thesequencer• Implements signal-levelprotocoland sends to the DUT• Virtual Interface –Connectionfrom the testbench to theDUT• Contains DUT signals for adeviceDUTMonitorCoverageCheckingviftlm i/fAPB IF• Independently collectstransactionsfrom the DUT interface• Contains events, status,checkingand coverage• Sends transactions to ascoreboardvia TLM write port• SystemVerilog Interface• Contains DUT bus signals• Encapsulates thecomponents fora device on the bus• Contains shared configinformation• A bus protocol can have avariable number of devices• Each is represented as an agent• An env encapsulates andconfigures multiple agents• Also referred to as an UVMVerification Component (UVC)
  8. 8. 88What Are the Benefits Of ThisArchitecture?UVC (UVM Verification Component)Master AgentSequencersequencestlm i/fDriverviftlm i/fCollectorviftlm i/fConfig:Slave AgentSequencersequencestlm i/fDriverviftlm i/fDUTAPB IFPassiveArchitecture exactly thesame across all languages!Encapsulating components makesit modular and simplifies maintenance“Virtual” sequences enablecontrol at the system levelControl and configurefrom above Easy-to-use testwriter interfaceSupports module-to-system reuseConfig:activeEach component has an UVM parent classwith built-in utilities and automation …Monitortlm i/ftlm i/fCollectorviftlm i/fMonitortlm i/ftlm i/fConfig:Config:passive
  9. 9. 9Agenda General Overview of UVM Challenges in using UVM at SoC level Proposal for using UVM at SoC level
  10. 10. 10 Quick setup of SoC verification env (integration ofall verification component) Synchronization or Control of verificationcomponents More emphasize is on system scenarios/integration rather than on randomization Should able to reuse configuration of IP from IPor sub-system testcases Should able to re-produce validation issuesChallenges for SoC verification
  11. 11. Reference IPUVM Verification Flow User CodeTLM PlatformIO InjectorReceiverReferenceIPVerificationSoCIntegrationSoC ValidationICNMemoryVirtual RegisterI/O UVCSequencerTLMDriverMonitorSeqsSeqsSeqsICN UVCSequencerTLMDriverMonitorSeqsSeqsSeqsVirtualSequenceRTL IPReference IPProtocolDriverProtocolDriverMonitorTLM PortMonitorTLM Port
  12. 12. RTL IPUVM Verification Flow at SoC level User CodeTLM PlatformIO InjectorReceiverReferenceIPVerificationSoCIntegrationSoC ValidationICNMemoryVirtual RegisterI/O UVCSequencerDriverMonitorSeqsSeqsSeqsICN UVCSequencerDriverMonitorSeqsSeqsSeqsProcessorNo Simple way to control UVC from C
  13. 13. 13Challenges in using UVM at SoC level No good way to control UVC from C or processor No standard way to support multiple language(available from Cadence but not Accellera orIEEE standard) Easier said than done to reuse the test cases(sequences) from IP->sub-system->SoC.
  14. 14. Proposed UVC Architecture… User CodeTLM PlatformIO InjectorReceiverReferenceIPVerificationSoCIntegrationSoC ValidationI/O UVCSequencerTLMDriverMonitorSeqsSeqsSeqsTLM 2.0 ExportProcessor Controlled SeqRegRegRegSequence Name RegControl Reg
  15. 15. 15Work done Developed a wrapper to connect TLM portbetween SystemC and UVM Added TLM export in sequencer Added a sequence with registers which can becontrolled through TLM port Developed Test platform to demonstratecontrolling of sequence from TLM IP
  16. 16. RTL IP3SoC Verification with UVM User CodeTLM PlatformIO InjectorReceiverReferenceIPVerificationSoCIntegrationSoC ValidationICNTLM ChannelEMITest Code (in C)TransactorUSBEthernetTLM RTL User Code Transactor (Sc or SCEMI)UVCIOInjectorReceiverSOCLMISLMUSBEthernetISSBFMUVCUVCPCITx/Rx Frame
  17. 17. 17Workdone Connection of EMI interface with SystemC TLMchannel Connection of TLM SystemC port with UVM port Developed Test Platform to demonstratecontrolling of sequence from Processor C code running on ISS, which is writing to a TLMPort about the sequence information Based on the received information, UVCsequence runs the required sequence orgenerate the random/directed traffic Checked the generated data through C testcase
  18. 18. 18 UVM good at IP level and best with standardinterfaces like AHB, AXI etc Best for constraint randomization verification Good in reusing verification components (likedriver, monitor or agents) For efficient reuse verification engineers need tobe expert in UVM and OOPs concept Still some gray areas for how to use UVM at SoCand Accellera can work in this areaMy view….
  19. 19. 19Wishlist for UVM 2.0 Seamless connection between UVM and SystemC ports TLM export in sequencer library Sequence with registers which can be written from TLMport in sequencer Event queue in sequencer for synchronization Standard name for some of the sequences likegenerate_interrupt, clear_interrupt, dma_data_transferetc
  20. 20. 20Thanks