PCI Express VerificationusingReference ModelingPCI Express VerificationusingReference ModelingAsad Khan and Scott Morrison...
2DUTPurposePurposeCPUCPURoot ComplexRoot ComplexPCIe™ EndpointPCIe™ EndpointPCI Express toPCI BridgePCI Express toPCI Brid...
3OutlineOutline• The Device Under Test (DUT)• Reference Model Example: Ingress Port Logic• Reference Model Example: Router...
4What is a Reference Model?What is a Reference Model?• A model that is independent of DUT implementation• Coded in high-le...
5PCI Express SwitchPCI Express SwitchPIPERXTXPIPETXRXPIPERXTXPIPERXTXPacket CrossbarRouter CrossbarDe-queue CrossbarPCIe P...
6The DUTThe DUT• The DUT (or DUTs, depending how we slice it up)• Customer deliverable: 4-port Switch ASIC• Large building...
7Design for Verification (DFV)Design for Verification (DFV)• Minimize side band controls• Use a standard bus for module in...
8Module and Chip Verification StrategyModule and Chip Verification Strategy• Bottom-up methodology• Reusable• Constrained-...
9A Look at Chip-level Prediction ModelA Look at Chip-level Prediction ModelDownPort 0DownPort 1DownPort 2UpPortTIPCIe eVCE...
10Chip-level Prediction Model: Closer lookChip-level Prediction Model: Closer lookDownPort 0RFMeIPL RFMDL RFMEPL RFMSchedu...
11IPL: Verification ChallengesIPL: Verification Challenges• All incoming packets buffered at input• Infinite memory space ...
12IPL DUT: How to verify?IPL DUT: How to verify?DLL TLPProcessorIngress Access Port (IAP)TLP CrossbarDLL TLP InterfaceRout...
13IPL Reference Model ArchitectureIPL Reference Model Architectureu_irxINTPKTRXu_erxEXTPKTRXu_epreprocEXT-PACKETPREPROCESS...
14Reference Model FeaturesReference Model Features• Cycle and Packet Accuracy (Hybrid Modeling)• Cycle accurate route toke...
15IPL Reference Model Architecture (cont.)IPL Reference Model Architecture (cont.)u_irxINTPKTRXu_erxEXTPKTRXu_epreprocEXT-...
16Reference Modeling TechniquesReference Modeling Techniques• Sub-function blocks coded as a high level units• Communicati...
17Reference Modeling Techniques (cont.)Reference Modeling Techniques (cont.)• Generic data collection monitors for all spe...
18Coverage and Debug MessagesCoverage and Debug MessagesIPL RFMIPL RFMfunctional coveragefunctional coverage
19Coverage and Debug Messages (cont.)Coverage and Debug Messages (cont.)[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: ===========...
20• Verification Planning• Preparation• Analyze all the relevant documents• Make sure you have the right people invited to...
21UpstreamIngressPortUpstreamEgressPortSchedulerRS0 RS2 RS2 RS2 RS1 RS1Upstream Port and Global Control Logic (GCL)Ingress...
22Router RFM: Why?Router RFM: Why?PCI Express LiteraturePCI Express Base SpecificationPCI Express to PCI Bridge Specificat...
23Router RFM: Why? (cont.)Router RFM: Why? (cont.)Specifications(1724 pages)Verilog codinge codingCo-SimulationRTL DUTHigh...
24Router eRM ArchitectureRouter eRM ArchitectureUpstreamIngressPortUpstreamEgressPortSchedulerRS0 RS2 RS2 RS2 RS1 RS1Upstr...
25TYPE1’hdr_typeMULTIFUNCTION’modepexrtr_env_uDOWNSTREAM’mode pexrtr_env_uUPSTREAM’modepexrtr_env_uTYPE0_EHCI’hdr_typeTYPE...
26Router eRM EnvironmentRouter eRM EnvironmentDownstream Port Router “e” EnvironmentVerilog DUTSlaveDNSelfSlaveDNPeer0Slav...
27Router RFM Comparison LogicRouter RFM Comparison Logic“e” RFM Token Comparison Unitpexrtr_rfm_compare_uin_token : pexrtr...
28Techniques of Router RFMTechniques of Router RFM• Cycle accurate• when inheritance plug-in rule sets• Simulation of pseu...
29Moving to chip levelMoving to chip level• Building blocks• Multiple RFMs• 4 instances of TI PCIe eVC• Top-level register...
30PCIe Port Reference ModelPCIe Port Reference ModelRTL eIPL RFMDL RFMEPL RFMIPL DUTDL DUTEPL DUTScheduler RFMScheduler DU...
31Finished Chip-Level Prediction ModelFinished Chip-Level Prediction ModelDownPort 1DownPort 2TIPCIe eVCEndpointTIPCIe eVC...
32ConclusionsConclusions• Architecture definition to facilitate Design forVerification• RFM methodology requires dedicated...
33Conclusions (cont.)Conclusions (cont.)• RFM will provide dual, independent interpretation ofspecification• RFM styles: C...
34Let’s talkLet’s talkQuestions? Thoughts?
35About the AuthorsAbout the Authors• Asad Khan (a-khan1@ti.com)• Lead Design Verification Engineer for 1394 and PCI Expre...
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PCI Express Verification using Reference Modeling

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PCI Express Verification using Reference Modeling

  1. 1. PCI Express VerificationusingReference ModelingPCI Express VerificationusingReference ModelingAsad Khan and Scott MorrisonJanuary 23, 2007Texas Instruments IncorporatedASIC / Backplane IP Development
  2. 2. 2DUTPurposePurposeCPUCPURoot ComplexRoot ComplexPCIe™ EndpointPCIe™ EndpointPCI Express toPCI BridgePCI Express toPCI BridgePCIe EndpointPCIe Endpoint4-portPCI ExpressSwitch• We will present– Modeling techniques for thecomplete verification of a PCIExpress® Switch– Our use of Specman eRM– Block-level to chip-level re-use
  3. 3. 3OutlineOutline• The Device Under Test (DUT)• Reference Model Example: Ingress Port Logic• Reference Model Example: Router• Integration of Reference Models at chip-level• Conclusions
  4. 4. 4What is a Reference Model?What is a Reference Model?• A model that is independent of DUT implementation• Coded in high-level, human-readable language• Cycle-accurate prediction where necessary• Because of maintenance overhead• Able to be co-simulated with the DUT to predict andcheck the runtime behavior• The auto-checking RFM+DUT simulationenvironment makes use of directed-random stimulus• “Let the machine do the work”
  5. 5. 5PCI Express SwitchPCI Express SwitchPIPERXTXPIPETXRXPIPERXTXPIPERXTXPacket CrossbarRouter CrossbarDe-queue CrossbarPCIe PHYPCIe PHYPCIe SwitchGlobalControlPCIe PHYPCIeDL / MACPCIe SwitchDownstreamTLPCIe PHYPCIeDL / MACPCIe SwitchDownstreamTLSEPLRPCIeDL / MACSRIPLPCIe SwitchUpstreamPortPCIe SwitchDownstreamPortIPLEPLPCIeDL / MACSRIPL Ingress Port LogicSchedulerRouterEgress Port LogicLegendEPL
  6. 6. 6The DUTThe DUT• The DUT (or DUTs, depending how we slice it up)• Customer deliverable: 4-port Switch ASIC• Large building blocks (verified at module level)• Data Link Layer• Ingress Port Memory• Router• Scheduler• Small building blocks• Power management• GPIO• Hot plug• Advanced Error Reporting• And more…
  7. 7. 7Design for Verification (DFV)Design for Verification (DFV)• Minimize side band controls• Use a standard bus for module interfaces• Standard BFM needed for module simulations• Add DFV signals to reduce verification complexity• Limited variability of pipe-line timing• Limit the number of building blocks• Re-use some blocks even though it is overkill
  8. 8. 8Module and Chip Verification StrategyModule and Chip Verification Strategy• Bottom-up methodology• Reusable• Constrained-random stimulus• Reference Models (RFMs) for automated checking• Hybrid approach• Control paths: cycle-accurate modeling• Data paths: packet-accurate modeling• Integration of models for chip-level prediction• Rigorous testing of linked list management, data link layer,routing, and arbitration logic• Some directed testing required
  9. 9. 9A Look at Chip-level Prediction ModelA Look at Chip-level Prediction ModelDownPort 0DownPort 1DownPort 2UpPortTIPCIe eVCEndpointTIPCIe eVCEndpointTIPCIe eVCEndpointTIPCIe eVCRoot ComplexPCIe Switch DUTDownPort 0RFMDownPort 1RFMDownPort 2RFMUpPortRFMSwitch Prediction ModelCycle-accurate andPacket-accurateDUT stimulus Switch reference modelSupportingChip-levelScoreboardScoreboards
  10. 10. 10Chip-level Prediction Model: Closer lookChip-level Prediction Model: Closer lookDownPort 0RFMeIPL RFMDL RFMEPL RFMScheduler RFMRouter RFMEgressTLPTX TLPPCIe Switch PortReference ModelPredictorCycle accurate control pathPacket-accurate data pathRX TLP
  11. 11. 11IPL: Verification ChallengesIPL: Verification Challenges• All incoming packets buffered at input• Infinite memory space challenge• Dynamic link list for en-queue/de-queue of packets• Dual mode support with dynamic behaviors• Cut-through & Store-and-Forward• Aggregation of traffic without back-pressure• Support for normal as well as error packets• Scalability for up to 9 simultaneous de-queues• Support for all permutations of throughputs• Among available ports (x1, x2 and x4)
  12. 12. 12IPL DUT: How to verify?IPL DUT: How to verify?DLL TLPProcessorIngress Access Port (IAP)TLP CrossbarDLL TLP InterfaceRouteMasterRoute CrossbarTLPStatusMemoryInternal TLPProcessorTLP StatusListCreditCountersInternal TLP InterfaceDLL Credit InterfaceTLP ProcessorData BufferDe-QueueCrossbarMemory SlotControllerDLLSYNCFIFOTLP ArbiterBroadcastCountMemoryTLP MemoryTLPMemoryList9 egress portsMixed trafficDual mode
  13. 13. 13IPL Reference Model ArchitectureIPL Reference Model Architectureu_irxINTPKTRXu_erxEXTPKTRXu_epreprocEXT-PACKETPREPROCESSOR(CYCLE-ACCURATE)+ERROR DETECTORu_ipreprocINT-PKTPREPROCESSORu_ellmExternal-PacketLink List Manageru_illmInternal-PacketLink List Manageru_dq_mgrDQManagerPORT1PORT2PORT9PORT3u_pkt_sorterPacketSORTERECRC MALF MISCERROR HEADER SCOREBOARDSu_rthdr_drvROUTE HEADERDRIVERu_rthdr_scbROUTE HEADER CYCLEACCURATE SCOREBOARDu_rabRTHDRARBe-Code High Level RFM Data Flowu_cfrCTRLCFRI/FDATA SCOREBOARDSe Link-List ModelF G E M N PORT1F G E M N PORT2F G E M N PORT9REG
  14. 14. 14Reference Model FeaturesReference Model Features• Cycle and Packet Accuracy (Hybrid Modeling)• Cycle accurate route token modeling for chip-level DV• Packet accurate modeling for packet transmission path• Modular Verification Architecture• Scalability for switch derivatives• Pointer Management Scheme• Independent of Hardware Implementation• Re-usable
  15. 15. 15IPL Reference Model Architecture (cont.)IPL Reference Model Architecture (cont.)u_irxINTPKTRXu_erxEXTPKTRXu_epreprocEXT-PACKETPREPROCESSOR(CYCLE-ACCURATE)+ERROR DETECTORu_ipreprocINT-PKTPREPROCESSORu_ellmExternal-PacketLink List Manageru_illmInternal-PacketLink List Manageru_dq_mgrDQManagerPORT1PORT2PORT9PORT3u_pkt_sorterPacketSORTERECRC MALF MISCERROR HEADER SCOREBOARDSu_rthdr_drvROUTE HEADERDRIVERu_rthdr_scbROUTE HEADER CYCLEACCURATE SCOREBOARDu_rabRTHDRARBe-Code High Level RFMu_cfrCTRLCFRI/FREGDATA SCOREBOARDSe Link-List ModelF G E M N PORT1F G E M N PORT2F G E M N PORT9
  16. 16. 16Reference Modeling TechniquesReference Modeling Techniques• Sub-function blocks coded as a high level units• Communication between units done through ports• A top-level unit binds all the sub-units through ports• Data communicated using structs through ports• Simulator callbacks reduced by using single eventfrom top-level unit fanned out to sub-units• Cycle-accurate information driven through HDLsignals between RFMs
  17. 17. 17Reference Modeling Techniques (cont.)Reference Modeling Techniques (cont.)• Generic data collection monitors for all speeds• Units coded under eRM guidelines• Design for Verification signals to avoid redundantmodeling• Hybrid modeling to reduce maintenance overhead
  18. 18. 18Coverage and Debug MessagesCoverage and Debug MessagesIPL RFMIPL RFMfunctional coveragefunctional coverage
  19. 19. 19Coverage and Debug Messages (cont.)Coverage and Debug Messages (cont.)[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: =================================[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: DUT TLP : MWr DW4_WD[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: RFM TLP : MWr DW4_WD[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: =================================[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: =============================[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: RFM POINTER 2[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: =============================[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: IAP4 FULL LIST SCOREBOARD[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: =============================[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: RFM DUT[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: byte byte[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: =============================[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 60 60[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 0 0[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: b0 b0[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: a a[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 1 1[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 0 0[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 2 2[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: ff ff[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 12 12[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 34 34[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 56 56[2712 ns] IPL_RFM_IAP_GEMN_SCOREBOARD: 78 78IPL RFMIPL RFMdebug messagesdebug messages
  20. 20. 20• Verification Planning• Preparation• Analyze all the relevant documents• Make sure you have the right people invited to themeeting• Brainstorming session• Capture non-specification coverage• Clarify specification ambiguities/issuesDUTDUTFunctional / DesignSpecificationsCadence vPlan used for IPL VerificationCadence vPlan used for IPL Verification
  21. 21. 21UpstreamIngressPortUpstreamEgressPortSchedulerRS0 RS2 RS2 RS2 RS1 RS1Upstream Port and Global Control Logic (GCL)IngressPortEgressPortSchedulerRS3AInternal Endpoint FunctionOHCI USBIngressPortEgressPortSchedulerRS4 RS5 RS6 RS6DownstreamPCIe Port 0RR0 RR1ARR2GCLEgressPortGCLIngressPortRS7 RS8IngressPortEgressPortSchedulerRS3BInternal Endpoint FunctionEHCI USBRR1B RS8RS9IngressPortEgressPortSchedulerRS4 RS5 RS6 RS6DownstreamPCIe Port 1RR2 RS9IngressPortEgressPortSchedulerRS4 RS5 RS6 RS6DownstreamPCIe Port 2RR2 RS9Distributed Routers: “SuperRouter”Distributed Routers: “SuperRouter”TLPRouteTokenSchedulertoken
  22. 22. 22Router RFM: Why?Router RFM: Why?PCI Express LiteraturePCI Express Base SpecificationPCI Express to PCI Bridge SpecificationPCI LiteraturePCI Local Bus SpecificationPCI-to-PCI Bridge SpecificationPCI Bus Power Management SpecificationTI Functional SpecificationsFunctional Spec for PCIe SwitchFunctional Spec for Multifunction PCIe DeviceDirected test overload!RTL SpecificationsPCI Express Switch Implementation SpecificationRouter Implementation Specification1724 pages of specifications++++
  23. 23. 23Router RFM: Why? (cont.)Router RFM: Why? (cont.)Specifications(1724 pages)Verilog codinge codingCo-SimulationRTL DUTHigh level RFMInterpretation CompareCycle accurate comparison
  24. 24. 24Router eRM ArchitectureRouter eRM ArchitectureUpstreamIngressPortUpstreamEgressPortSchedulerRS0 RS2 RS2 RS2 RS1 RS1Upstream Port and Global Control Logic (GCL)IngressPortEgressPortSchedulerRS3AInternal Endpoint FunctionOHCI USBIngressPortEgressPortSchedulerRS4 RS5 RS6 RS6DownstreamPCIe Port 0RR0 RR1ARR2GCLEgressPortGCLIngressPortRS7 RS8IngressPortEgressPortSchedulerRS3BInternal Endpoint FunctionEHCI USBRR1B RS8RS9IngressPortEgressPortSchedulerRS4 RS5 RS6 RS6DownstreamPCIe Port 1RR2 RS9IngressPortEgressPortSchedulerRS4 RS5 RS6 RS6DownstreamPCIe Port 2RR2 RS9
  25. 25. 25TYPE1’hdr_typeMULTIFUNCTION’modepexrtr_env_uDOWNSTREAM’mode pexrtr_env_uUPSTREAM’modepexrtr_env_uTYPE0_EHCI’hdr_typeTYPE1’hdr_type TYPE0_OHCI’hdr_typeRouter eRM Architecture (cont.)Router eRM Architecture (cont.)RS0 RS2 RS2 RS2 RS1 RS1 RS3ARS4 RS5 RS6 RS6RR0 RR1ARR2RS7 RS8 RS3ARR1ARS8RS9 RS4 RS5 RS6 RS6RR2 RS9 RS4 RS5 RS6 RS6RR2 RS9
  26. 26. 26Router eRM EnvironmentRouter eRM EnvironmentDownstream Port Router “e” EnvironmentVerilog DUTSlaveDNSelfSlaveDNPeer0SlaveDNPeer1SlaveUPPeerRegisters e RFMdn_to_self’slave_typedn_to_dn’slave_typedn_to_dn’slave_typeup_to_dn’slave_typeTYPE1’hdr_typereg_uTokenBFMTokenBFMTokenBFMTokenBFMTokenSBTokenSBTokenSBTokenSBConfigBFMSideband SignalBFMsDOWNSTREAM’kind TYPE1’hdr_typeTRUE’has_reference_model pexrtr_env_u
  27. 27. 27Router RFM Comparison LogicRouter RFM Comparison Logic“e” RFM Token Comparison Unitpexrtr_rfm_compare_uin_token : pexrtr_token_s;event in_token_done_e;rfm_token : pexrtr_sch_token_s;event rfm_token_done_e;env : pexrtr_env_u;bus_name : pexrtr_bus_name_t;slave_type : pexrtr_rfm_slave_t;From inputmonitor1) Daisy chain pre-processing sequential logic.2) Call compare_<type>_token() based on Memory, IO, etc.3) Daisy chain post-processing sequential logic.To outputscoreboardPlug-inrule sets
  28. 28. 28Techniques of Router RFMTechniques of Router RFM• Cycle accurate• when inheritance plug-in rule sets• Simulation of pseudo chip-level SuperRouter• Detailed log files of each transaction• RFM includes text comments explaining expectedbehavior:Bus mastering disabled, so ignore all Memory TLPs.Previously deemed Malformed. Ignore.In IO window. Blocked.Previously deemed UR.Completion is outside sec-to-sub window, and sec!=0, so claim it.Ignore all internally generated Vendor_Type1 MsgD messages.
  29. 29. 29Moving to chip levelMoving to chip level• Building blocks• Multiple RFMs• 4 instances of TI PCIe eVC• Top-level register model• Top-level predictor• Top-level scoreboard• Connect the dots• Using TLP ID• Uniquely identify every packet in the entire system for theentire simulation
  30. 30. 30PCIe Port Reference ModelPCIe Port Reference ModelRTL eIPL RFMDL RFMEPL RFMIPL DUTDL DUTEPL DUTScheduler RFMScheduler DUTRX DataRoute TokenScheduling TokenEPL TokenDQTokenRX TLPTLPIDEgressTLP TX TLPRouter RFMRouter DUTTLPIDTLPIDTLPIDEgressTLPTX TLPExample: Downstream Port
  31. 31. 31Finished Chip-Level Prediction ModelFinished Chip-Level Prediction ModelDownPort 1DownPort 2TIPCIe eVCEndpointTIPCIe eVCEndpointTIPCIe eVCEndpointIngressTLPsDown Port 2TLP Ingr ListDown Port 1TLP Ingr ListDown Port 0TLP Ingr ListUp PortTLP Ingr ListIngressListsearchalgorithmUp PortTLP Pred FIFODown Port 0TLP Pred FIFODown Port 1TLP Pred FIFODown Port 2TLP Pred FIFOTLPCheckTLPCheckTLPCheckTLPCheckTLP ID from each Port Scheduler RFMUp Ingress TLPPCIe Switch DUTDownPort 1RFMDownPort 2RFMSwitch Prediction ModelCycle-accurate andpacket-accurateEgressTLPsConfigurationSpace Register ModelAndCompletion Predictor1) TLP Ingress2) TLP Switching3) TLP EgressDownPort 0UpPortTIPCIe eVCRoot ComplexDownPort 0RFMUpPortRFM
  32. 32. 32ConclusionsConclusions• Architecture definition to facilitate Design forVerification• RFM methodology requires dedicated andspecialized Verification Engineer resources• Rigorous block-level simulation permitted 2 daysfrom integration to first chip-level simulation• 2-weeks of chip-level simulations put robust FPGAbuild in the lab for emulation• “SuperRouter” simulations eliminatedlost/misdirected packets at chip-level• Silicon had outstanding performance at Plug Festsand has shown no bugs in RFM features
  33. 33. 33Conclusions (cont.)Conclusions (cont.)• RFM will provide dual, independent interpretation ofspecification• RFM styles: Choose wisely• cycle accurate, packet accurate, hybrid• Muscle of Specman random generation is only asgood as the auto-checking features of testbench• RFM hookup at chip-level:• Identify hookup issues, interface violations• Check for chip-level stimulus that was missed at module-level• Chip-level debug acceleration
  34. 34. 34Let’s talkLet’s talkQuestions? Thoughts?
  35. 35. 35About the AuthorsAbout the Authors• Asad Khan (a-khan1@ti.com)• Lead Design Verification Engineer for 1394 and PCI Expressproducts• Scott Morrison (scott@ti.com)• Lead Design Verification Engineer for Mixed Signal IP, includinghigh-speed SERDES, USB 2.0 PHY, and 1394 PHYWe would appreciate feedback. Feel free to contact us.

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