The document discusses microprocessors and the Intel 8086/88 microprocessor. It provides details on the key components and architecture of microprocessors including the register set, addressing modes, buses, and evolution of 8-bit microprocessors. It describes the features of the Intel 8086/88 including its 20-bit address bus, 14 16-bit registers, 9 addressing modes, and segmented memory address space.
2. MICROPROCESSOR
• THE MAIN COMPONENT OF ANY DIGITAL
COMPUTER
• THE BRAIN OF THE SYSTEM, AS IT
CONTROLS AND COORDINATES ALL THE
ACTIVITIES THAT ARE PERFORMED BY THE
SYSTEM
• ESSENTIAL FUNCTION- TO IMPROVE THE
EFFICIENCY OF THE PROCESS
3. MICROPROCESSOR
• A GREAT INVENTION
• CPU ON A CHIP
• IT CHANGED THE ENTIRE CONCEPT OF
DIGITAL SYSTEM DESIGN, AS THE
ADDRESSING SUBSYSTEM HAS BEEN
INCORPORATED ON THE CHIP ITSELF
• ALU + CU
5. MICROPROCESSOR
• IT IS MICRO IN TERMS OF ITS SIZE AND
COST ONLY, NOT IN ITS CAPABILITY
• THE SPEED OF THE SYSTEM IS MEASURED
IN MIPS/MFLOPS
• USING 80386DX, PERFORMANCE OF MORE
THAN 1 MIPS CAN BE EASILY ACHIEVED
6. MICROPROCESSOR
• WITH ITS PROGRESS, EITHER THE
MAINFRAME SHOPS CLOSED DOWN
OR THEY SWITCHED TO
MANUFACTURING WORKSTATIONS
• ITS USE IS ONLY LIMITED BY HUMAN
THOUGHT
• IT CAN BE APPLIED ANYWHERE
7. MICROPROCESSOR
• EVERY MICROPROCESSOR HAS:
3 VITAL SETS OF LINES, KNOWN AS BUSSES SEPARATELY
AVAILABLE : ADDRESS BUS, DATA BUS AND CONTROL BUS.
ADDRESS BUS IS UNIDIRECTIONAL, DATA BUS IS
BIDIRECTIONAL AND CONTROL BUS IS QUASI BIDIRECTIONAL
ADDRESS BUS
DATA BUS
CONTROL BUS
STATUS LINES
CONTROL LINE
MICRO
PROCES
SOR
8. MICROPROCESSOR
ADDRESS BUS
UNIDIRECTIONAL FOR THE PURPOSE OF
SYNCHRONIZATION
IT POINTS TOWARDS ANY BLOCK THAT IS
INTERFACED WITH IT
IT TELLS US ABOUT THE SIZE OF THE
MEMORY MAP OF THE PROCESSOR
TELLS US ABOUT THE SIZE OF PRIMARY
MEMORY THAT CAN BE INTERFACED WITH
THE PROCESSOR
10. MEMORY MAP
• MAP OF ALL POSSIBLE PHYSICAL
ADDRESSES
ROM
RAM
SYSTEM AREA
USER AREA
11. MICROPROCESSOR
EVERY MICROPROCESSOR HAS:
ITS OWN MEMORY MAP
ITS OWN INSTRUCTION SET
ITS OWN ADDRESSING MODES
THE NUMBER OF WAYS IN WHICH IT CAN ACCESS
DATA/INSTRUCTIONS FROM EITHER ITS INTERNAL
REGISTERS OR EXTERNAL MEMORY
THE MORE IS THE NUMBER OF WAYS AVAILABLE, THE
MORE IS THE POWER OF THE PROCESSOR
12. MICROPROCESSOR
• IMPLEMENTATION BASED ON
- BINARY LOGIC
- USE OF BASIC LOGIC ELEMENTS
- A STORED INST OR CONTROL SEQUENCE
- USE OF ADDRESSING TO CONTROL THE COMM ROUTE
BETWEEN THE DEVICES OF A SYSTEM
• ABILITY TO – FETCH & EXECUTE A LIMITED SET OF INSTS.
- TO INPUT AND OUTPUT BINARY DATA
• MEANS OF MEASURING THE PROCESSOR
- WIDTH & DRIVE CAPABILITY
- CONTROL BUS, FOR MEMORY & INTERFACE DEVICES
13. MICROPROCESSOR
• THE EXECUTION OF ANY PROGRAM IN ANY
MICROPROCESSOR CONSISTS ENTIRELY OF READ AND
WRITE OPERATIONS WHERE EACH RD AND WR OPERATION
TRANSFERS A DATA BYTE BETWEEN A MICROPROCESSOR
AND A PARTICULAR MEMORY OR I/O DEVICE ADDRESS
• EACH READ OR WRITE OPERATION IS REFERRED TO AS
MACHINE CYCLE.
• THE EXECUTION OF EACH INST CONSISTS OF A SEQUENCE
OF MACHINE CYCLES AND EACH MACHINE CYCLE CONSISTS
OF SEVERAL CLOCK CYCLES
• INST CYCLE = FETCH CYCLE + EXECUTE CYCLE
14. ELEMENTS OF A MICROPROCESSOR
ESSENTIAL ELEMENTS
INSTRUCTION REGISTER
INSTRUCTION DECODER
CONDITION CODE REGISTER/FLAG REGISTER/STATUS REG.
CONTROL ROM
ALU
CONTROL AND TIMING SECTION
ACCUMULATOR
PROGRAM COUNTER
CLOCK GENERATOR
15. ELEMENTS OF A MICROPROCESSOR
NON-ESSENTIAL ELEMENTS:
GENERAL PURPOSE REGISTERS
INDEX REGISTERS
STACK POINTER
INTERRUPT PRIORITY ARBITRATION, BARREL SHIFTER
DMA CONTROL LOGIC
TRANSLATION LOOKASIDE BUFFER,ETC.
-----------------------------------------------------
IF WE ADD ANY OR ALL OF THESE : QUANTIZER, RAM, ROM,
COUNTER/TIMER, I/O PORTS, ETC. THEN IT IS CALLED A
MICRO-CONTROLLER . DESIGN OF A MICRO-CONTROLLER IS
A STEP TOWARDS MINIATURIZATION.
16. 8-BIT MICROPROCESSORS
IT BEGAN WITH INTEL 8008
• 8080, 8085
• MOTOROLA 6800
• ZILOG Z-80
• MOSTEK 6502
• FAIRCHILD F-8
• ETC.
17. INTEL 8080
• REGISTER ARCHITECTURE
8 BITS
16 BITS
A
B C
D E
H L
PROGRAM COUNTER
STACK POINTER
FLAGS
ACCUMULATOR
GENERAL PURPOSE REGISTERS
SIGN, ZERO, CARRY, AUX CARRY,
PARITY
• 40 PIN DIP CHIP
•3 CHIP PROCESSOR – ONE NEEDS 8224 AND 8228
•8224 IS THE CLOCK GENERATOR AND 8228 IS THE SYSTEM BUS CONTROLLER
•NEEDS +5V, +12V AND -12V POWER SUPPLIES
•78 INSTRUCTIONS IN ITS INSTRUCTION SET
•ADDRESSING MODES: REGISTER, IMMEDIATE, IMPLIED, DIRECT, INDIRECT,
COMBINED
18. INTEL 8085
• REGISTER ARCHITECTURE SAME AS THAT OF 8080
• ADDRESSING MODES SAME AS THAT OF 8080
• 40 PIN DIP CHIP
• REQUIRES ONLY +5V SUPPLY
• SYSTEM CONTROLLER AND CLOCK GENERATOR ON CHIP;
EVEN THEN IT IS A 2 CHIP PROCESSOR
• BECAUSE THE LOWER HALF OF THE ADDRESS BUS HAS
BEEN MULTIPLEXED WITH THE DATA BUS – SO NEEDS TO BE
DEMULTIPLEXED FOR WHICH WE NEED 8212
• PROVIDES VECTORED INTERRUPTS – RST5.5, 6.5, 7.5 AND
TRAP
• 80 INSTRUCTIONS IN ITS INSTRUCTION SET – RIM, SIM
19. INTEL 8085
MINIMUM CONFIGURATION
8085
8212
AD0-
AD7
ALE
DEN’
D0-D7
A8-A15
A0-A7
RST 5.5
RST 6.5
RST 7.5
TRAP
MASKABLE
VECTORED
INTERRUPTS
NON-MASKABLE
VECTORED INTERRUPT
SID
SOD
• RIM- RESET INTERRUPT MASK
•SIM – SET INTERRUPT MASK
•RST n – 8 X n eg., RST 5.5 – 8 X 5.5 =(44)10 = (2C)16 ie., IT TAKES
THE PROGRAM COUNTER TO THE LOCATION 002C
16 BIT ADDRESS BUS
20. MOTOROLA 6800
• REGISTER ARCHITECTURE
8 BITS
16 BITS
ACC A
ACC B
PROGRAM COUNTER
STACK POINTER
INDEX REGISTER
FLAGS C,S,Z,AC,P
•40 PIN DIP CHIP
•NO GENERAL PURPOSE REGISTER, BUT MAKES FOR THE
DEFICIENCY BY HAVING 2 ACCS AND INDEX REG.
•ADDRESSING MODES: IMPLICIT, DIRECT, INDIRECT,
INDEXED, COMBINED
•72 INSTRUCTIONS
•AS NO GPR, MEM. REFERENCING NEEDED EVERYTIME
21. MOTOROLA 6800
INTERRUPT HANDLING:
• (IRQ)’ : FFF8 & FFF9
- NOT BASICALLY DESIGNED FOR LARGE NO. OF INTERRUPTS
RST : FFFE & FFFF
(NMI)’ : FFFC & FFFD
SWI : FFFA & FFFB
- IT HAS SW INTERRUPT AND SAVES REGISTERS
AUTOMATICALLY ON AN INTERRUPT
- 6809 HAS AVOIDED THIS PROBLEM OF WASTAGE OF TIME IN
SAVING REG CONTENTS WHEN WE DO NOT WANT TO BY
PROVISING (FIRQ)’
- ALL THESE ARE POLLED INTERRUPTS , NOT VECTORED
22. ADDRESSING MODES OF 8-BIT FAMILY
• IMPLIED/INHERENT
• REGISTER
• IMMEDIATE
• DIRECT
• INDIRECT
• COMBINED
• INDEXED
• RELATIVE/BRANCH
23. ADDRESSING MODES OF 8-BIT FAMILY
• IMPLIED/INHERENT:
THE ADDRESS IS INHERENT IN THE
INSTRUCTION OR THE FUNCTION OF THE
INSTRUCTION IS IMPLIED
IT DOES NOT NEED ANY DATA.
eg., STC, DAA
24. ADDRESSING MODES OF 8-BIT FAMILY
• REGISTER:
ONE OF THE REGISTERS (GPRs) HAS TO BE
SPECIFIED. WITH THESE INSTRUCTIONS THE
ACCUMULATOR IS IMPLIED TO CONTAIN THE
SECOND OPERAND.
eg., CMP E, ADD B, PCHL
25. ADDRESSING MODES OF 8-BIT FAMILY
• IMMEDIATE:
DATA IS A PART OF THE INSTRUCTION
OR DATA IS CONTAINED IN THE INSTRUCTION OR
THE OPERAND IMMEDIATELY FOLLOWS THE
OPCODE
eg., MVI A,24 ; CPI 04
26. ADDRESSING MODES OF 8-BIT FAMILY
• DIRECT:
THE OPERAND FIELD OF THE SOURCE
STATEMENT IS THE ADDRESS OF THE VALUE TO
BE OPERATED UPON. INSTRUCTION INCLUDES THE
DIRECT ADDRESS.
eg., LDA 2034 ; JMP 4260
IN # 04 ; OUT # 40
27. ADDRESSING MODES OF 8-BIT FAMILY
• INDIRECT:
IT REFERENCES MEMORY INDIRECTLY
VIA A REGISTER PAIR. SO, THE ADDRESS OF THE
OPERAND IS INDIRECTLY OBTAINED.
eg., MOV M,C ; MOV B,M
28. ADDRESSING MODES OF 8-BIT FAMILY
• COMBINED:
IT USES THE COMBINATION OF DIRECT
AND INDIRECT ADDRESSING.
eg., CALL 3424 Here 3424 is the direct
address. It gives the start address of the
subroutine. RET provides the return
address indirectly to go to the next address in the Main
Program wherefrom it had branched to the Subroutine.
29. ADDRESSING MODES OF 8-BIT FAMILY
• INDEXED:
CAN BE IMPLEMENTED ONLY WHEN THE
PROCESSOR HAS THE INDEX REGISTER.
SECOND BYTE OF THE INST IS A NO.
WHICH IS ADDED TO THE LOWER BYTE OF THE NO.
STORED IN THE INDEX REGISTER TO GET THE
EFFECTIVE ADDRESS.
eg., ADD A,X $02
30. ADDRESSING MODES OF 8-BIT FAMILY
• RELATIVE/BRANCH:
1ST BYTE IS THE INST AND THE SECOND
BYTE IS THE OFFSET ADDRESS WHICH IS ADDED
TO THE CONTENTS OF THE PC.
SINCE IT IS DESIRABLE TO BRANCH OUT
IN EITHER DIRECTION, THE MSB IS TAKEN AS THE
SIGN BIT. IF MSB=0, IT IS TAKEN AS +VE OR
BRANCH FORWARD, IF MSB=1, IT IS TAKEN AS –VE
OR BRANCH BACKWARDS. BY HOW MANY
LOCATIONS? – IS DETERMINED BY TAKING THE 2’S
COMPLEMENT OF THE GIVEN NUMBER.
eg., BRA $FD
31. 8086/88
• THE ARCHITECTURE IS BASED UPON THE
FOLLOWING PRINCIPLE:
ENTIRE HARDWARE IS NOT BURDENED FOR
SIMPLER OPERATIONS
HAS A SEGMENTED ADDRESS SPACE
CAN BE DIVIDED INTO TWO DISTINCT HALVES
32. 8086/88
• FEATURES:
40 PIN DIP CHIP
20 BIT AB, 16 BIT DB
SEGMENTED ADDRESS SPACE
14 NOS., 16-BIT REGISTERS
9 BASIC ADDRESSING MODES, 24 IN ALL
IMPLEMENTED USING N-CHANNEL, DEPLETION LOAD, Si-
GATE TECHNOLOGY (HMOS)
8& 16 BIT SIGNED AND UNSIGNED ARITHMETIC IN BINARY OR
DECIMAL INCLUDING MULTIPLY AND DIVIDE
34. 8086
• BLOCK DIAGRAM:
CONTROL & TIMING SECTION
DATA,
POINTER &
INDEX REGS
(8)
SEGMENT
REGS AND
INST POINTER
(5)
REG
FILE
EXEC.UNIT
BUS
INTERFACE
UNIT
REGISTER
RELOCATION
FILE
ALU
FLAGS
BIU
INST. QUEUE
AD0-AD15
A16-A19
BHE’/S7
INTA’,RD’,WR’
DT/R’, DEN’, ALE
TEST ’
NMI
INT ’
RG/GT’0,1 HLDA HOLD CLK RST RDY MN/MX’ GND(2),VCC
S0,S1,S2
QS0,QS1
(LOCK)’
35. 8086/88
• REGISTER ARCHITECTURE:
AH AL
BH BL
CH CL
DH DL
BASE POINTER
STACK POINTER
CODE SEGMENT REGISTER
DATA SEGMENT REGISTER
STACK SEGMENT REGISTER
EXTRA SEGMENT REGISTER
INSTRUCTION POINTER
SOURCE INDEX REGISTER
DESTINATION INDEX REGISTER
CONDITION CODE REGISTER
AX
BX
CX
DX
BP
SP
IP
SI
DI
T, I, D
P, C, S, Z, AC, O
38. 8086/88
• STATUS LINES:
S4 S3
0 0 ESR
0 1 SSR
1 0 CSR/NONE
1 1 DSR
• S5 IS UPDATED AT THE BEGINNING OF EACH CYCLE
• S6 IS ALWAYS ZERO
• S7 – LOW INDICATES THAT IT HAS GONE TO HOLD STATE
39. 8086/88
• QUEUE STATUS:
QS0 QS1
0 0 NO OPERATION
0 1 FIRST BYTE OF OPCODE FROM QUEUE
1 0 QUEUE IS EMPTY
1 1 SUBSEQUENT BYTE READ FROM QUEUE
40. 8086/88
• INSTRUCTION FORMAT:
D W
MOD
REG
R / M
LOW DISPLACEMENT HIGH DISPLACEMENT
OPCODE
D=0 FROM REG ; 1 TO REG MOD=11 R / M IS TREATED AS REG
MOD 11 00 01 10
000 AL/AX (BX)+(SI) +D8 +D16
001 CL/CX (BX)+(DI)
010 DL/DX (BP)+(SI)
011 BL/BX (BP)+(DI)
100 AH/SP (SI)
101 CH/BP (DI)
110 DH/SI (BP)
111 BH/DI (BX)
W=0 BYTE, ELSE WORD
S BIT : REPLACES D BIT
V BIT : REPLACES D BIT : 0, COUNT=1;
ELSE FROM CL REG.
Z BIT: REPLACES W BIT ; USED FOR
STRING PRIMITIVES FOR COMPARISON
WITH ZERO FLAG – STRING
MANIPULATION
42. 8086
• MEMORY MAP:
00000
0001300014
0007F 00080
FFFEFFFFF0
FFFFB FFFFC
FFFFF
RESERVED
DEDICATED
U
S
E
R
RESERVED
DEDICATED
For use with future products
For functions such as storage of
hardware reset jump instruction
128 bytes used for storage of pointers to
ISR.
Each pointer requires 4 bytes of
memory. 2 bytes hold the 16 bit segment
address and the other 2 hold the 16 bit
offset.
44. 8086
• ADDRESSING MODES:
1. REGISTER
2. IMMEDIATE
3. DIRECT
4. INDIRECT
5. BASED
6. INDEXED
7. BASED INDEXED
8. STRING
9. I/O PORT
45. 8086
1. REGISTER:
THE OPERAND TO BE ACCESSED IS SPECIFIED AS
RESIDING IN AN INTERNAL REGISTER OF 8086
MOV AX,BX
46. 8086
2. IMMEDIATE:
THE SOURCE OPERAND IS A PART OF THE INSTRUCTION.
THE VALUE OF THE IMMEDIATE OPERAND MUST BEGIN
WITH A NUMBER
MOV AL, 15
MOV BL, 0A5
47. 8086
3. DIRECT:
THE LOCATIONS FOLLOWING THE OPCODE HOLDS THE
EFFECTIVE ADDRESS
THIS EFFECTIVE ADDRESS IS A 16-BIT OFFSET OF THE
STORAGE LOCATION OF THE OPERAND FROM THE
LOCATION SPECIFIED BY THE CURRENT VALUE IN THE DS
REGISTER.
MOV CX, [BETA]
MOV BX,(1234)
48. 8086
4. INDIRECT:
IT IS SIMILAR TO DIRECT ADDRESSING IN THAT AN EA IS
COMBINED WITH THE CONTENTS OF DS TO OBTAIN A
PHYSICAL ADDRESS.
BUT, IT DIFFERS IN THE WAY THE OFFSET IS SPECIFIED.
HERE, THE EA RESIDES IN EITHER A BASE REG. (BX,BP)
OR AN INDEX REG. (SI,DI)
MOV AX,(SI)
MOV (BP),CX
49. 8086
5. BASED:
THE PHYSICAL ADDRESS OF THE OPERAND IS OBTAINED BY
ADDING A DIRECT/INDIRECT DISPLACEMENT TO THE CONTENTS
OF THE BASE REG. BX/BP AND THE CURRENT VALUE IN DS/SS
REG RESPECTIVELY
IF BP IS USED, INSTEAD OF BX, THE CALCULATION OF THE
PHYSICAL ADDRESS IS PERFORMED USING THE CONTENTS OF
SS REG. INSTEAD OF DS.
THIS PERMITS ACCESS TO DATA IN THE STACK SEGMENT OF THE
MEMORY
MOV (BX), AL ; MOV (BP)+ALPHA,CH
50. 8086
6. INDEXED:
IT IS IDENTICAL TO BASED ADDRESSING EXCEPT THAT IT
USES THE CONTENTS OF SI/DI INSTEAD OF BX/BP
EA IS FORMED BY ADDING THE OFFSET TO THE SHIFTED
CONTENTS OF DS ONLY
MOV AL, (SI)
MOV (DI) + BETA, AH
51. 8086
7. BASED INDEXED:
COMBINATION OF BASED AND INDEXED ADDRESSING
EA IS FORMED BY ADDING THE OFFSET TO THE SHIFTED
CONTENTS OF DS RGISTER ONLY
MOV AH,(BX)(SI)+BETA
MOV (BP)(DI),CL
52. 8086
8. I/O PORT ADDRESSING:
DIRECT AND INDIRECT
DIRECT : IN # , OUT # ; # CAN BE A 16 BIT NUMBER
INDIRECT: THROUGH REG DX ONLY
MOV DX, WWWW ; IN AL,DX
54. 80186
• BLOCK DIAGRAM:
BIU CSU
PROG.
DMA
UNIT
PROG.
TIMERS
PICU
16 BIT
ALU
16 BIT
GPRs
CLOCK
GENER
ATOR
EU
55. 80186
• FEATURES:
68 PIN (LCC, PLCC, PGA)
16 BIT DB : 80188 – 8 BIT DB
SINGLE CHIP MICROCONTROLLER FOR
EMBEDDED APPLICATIONS
8086+ PICU + TIMER/COUNTERS(3) + DMA
LOGIC(2) + WAIT STATE GENERATOR+
CLOCK FREQ GENERATOR
56. 80186
REGISTER ARCHITECTURE SAME AS 8086
INSTRUCTION SET : SIMILAR TO THAT OF 8086 + 10 NEW
INSTRUCTIONS : INS, OUTS, PUSHI, IMUL, PUSHALL, POPALL,
SHIFTI, ROTATEI, BOUND, ENTER/LEAVE
13 INTERNAL ADDRESS DECODERS WITH ONE CHIP SELECT
OUTPUT EACH FOR THE SELECTION OF SIX MEMORY AREAS
AND SEVEN PERIPHERAL UNITS
UPPER/LOWER/MIDRANGE MEM CS: MCS0-3, UCS, MCS
PERIPHERAL CHIP SELECT PCS0-4, PCS5, PCS6
57. 80186
• 2 ADDITIONAL TRAPS:
•
A. UNUSED OPCODE – USEFUL IN DETECTING
PROGRAM ERRORS AND PROVIDES A SET OF
OPCODES WHICH THE USER MAY DEFINE FOR
SPECIFIC PURPOSES, EMULATING THE ACTION
OF THE INSTRUCTION IN SOFTWARE.
B. ESCAPE OPCODE – IT GIVES INST TO
COPROCESSOR. THE PROGRAMMING IS DONE
BY A BIT IN THE RELOCATION REGISTER. IT IS
PROGRAMMED NOT TO CAUSE A TRAP ON
RESET.
58. 80186
• INTERRUPT FACILITIES:
80186 CAN HANDLE 256 DIFFERENT EXCEPTIONS AND THE
VECTORS FOR THESE ARE HELD IN THE VECTOR TABLE.
WHEN RUNNING IN THE REAL MODE, THE VECTOR TABLE
CONSISTS OF 4 BYTE ENTRIES FOR EACH VECTOR.
FOR THE PROTECTED MODE OPERATION, EACH VECTOR
ENTRY IS 8 BYTES LONG AND THESE ARE HELD IN THE
INTERRUPT VECTOR TABLE.
59. 80186
• VECTORS ARE ALLOCATED AS FOLLOWS:
VECTOR FUNCTION
5 ARRAY BOUND CHECK
6 INVALID/UNDEFINED OPCODE
7 DEVICE NOT AV/PROC.EXTN NOT AV
8 DOUBLE FAULT
9 COPROC SEG OVERRUN
10 INVALID TASK STATE SEGMENT
11 SEGMENT NOT PRESENT
12 STACK FAULT
13 GENERAL PROTECTION FAULT
14 PAGE FAULT
15 RESERVED
16 COPROC ERROR/ ESC OR WAIT
17-31 RESERVED
32-255 INT n – USER INTERRUPTS
60. 80286
• BLOCK DIAGRAM:
OFFSET
ADDER
SEG LIMIT
AND BASE
ADDR
PHYSIC
AL
ADDER
ALU
REGISTE
RS
CONTRO
L REG.
ADDRESS LATCHES
AND DRIVERS
BIU
DATA
TRANSCEIVERS
6 BYTE
PREFETCH
QUEUE
INST
DECODE
R
QUEUE OF
3
DECODED
INSTS.
61. 80286
• FEATURES:
ADVANCED 16-BIT MICROPROCESSOR
DESIGNED USING CHMOS III TECHNOLOGY FOR
MULTI-USER, MULTI-TASKING APPLICATIONS
REQUIRES LOW POWER (POWER DOWN MODE)
PROVIDES HIGH PERFORMANCE
62. 80286
HAS BUILT IN MEM PROTECTION – 4 LEVEL
PROTECTION MECHANISM FOR TASK
ISOLATION
HARDWIRED TASK SWITCHING FACILITY
MEM MANAGEMENT CAPABILITY FOR
MAPPING 230
BYTES VA INTO 224
BYTES PA
FLAGS :11 – NT, IOPL
63. 80286
• BASIC STRUCTURE IS SIMILAR TO 8086
• 68 PIN CHIP
• ENLARGEMENT OF THE BUS CONTROL UNIT
• REDUCTION AND OVERLAPPING OF BUS CYCLES
• SUPPORT OF SYSTEM WITH VIRTUAL MEMORY
64. 80286
• MULTIPLE ACCESS CONTROL BY MEANS
OF SEGMENT DESCRIPTORS AND OF FOUR
PROCESSOR OPERATION MODES THAT
ARE DIFFERENTLY PRIVILEDGED.
• IN REAL ADDRESS MODE, THE MMU IS
SWITCHED OFF – WORKS LIKE 8086
• INTERRUPT FACILITY SIMILAR TO THAT OF
80186
65. 80286
• NEW FLAGS:
IOPL – A 2-BIT FLAG – USED TO GUARANTEE THAT AN INST
PERFORMS ONLY THOSE OPERATIONS IT IS AUTHORIZED TO
PERFORM
NT – USED TO INDICATE WHETHER THE EXECUTION OF THE
CURRENT TASK IS NESTED WITHIN ANOTHER TASK. IF SET,
THE CURRENT NESTED TASK HAS A VALID LINK TO THE
PREVIOUS TASK.
66. 80286
• CONTROL REGISTER:
o 5 BITS – PE, MP, TS, EM AND ET – HAVE BEEN UTILIZED FOR
STORING THE MACHINE STATUS, TERMED AS MSW.
o PE – USED TO ACTIVATE THE PROTECTED MODE
o MP – USED ALONGWITH TS BIT TO DETERMINE WHETHER THE WAIT
OPCODE WILL GENERATE A COPROC NOT AV FAULT IF TS=1
o EM – IF SET, CAUSES ALL COPROC OPCODES TO GENERATE
COPROC NOT AV FAULT
o TS – AUTOMATICALLY SET ON TS. WITH TS SET A COPROC
OPCODE WILL CAUSE A COPROC NOT AV TRAP
o ET – INDICATES PROCESSOR EXTENSION TYPE
67. 80386
• BASIC BLOCK DIAGRAM:
P T U
REGISTERS
BARREL SHIFTER
MUL/DIV
A L U
SEGMENT
REGISTER
S
SEG.
TRANSLATOR
TRANSLATI
ON
LOOKASIDE
BUFFER
PAGE
TRANSLATOR
BUS
CONTROL
ADDRESS
DRIVER
PIPELINE/BU
S SIZE
CONTROL
MUX/TRANS
CEIVER
PREFETCH
QUEUE (16
BYTES)
PREFETCH
ER
DECODER
&
SEQUENCI
NG
INST QUEUE
(3 DECODED
INST)
CONTR
OL
ROM
EU
su
PU REQUEST
PRIORITIZER
BIU
DU
68. 80386
• FUNCTIONAL BLOCK DIAGRAM:
B I U
INST
PREFETCH
INST
PRECODE
CONTROL
ROM
A L U
BUS
CONTROL
PAGING
UNIT
SEGMENTATI
ON UNIT
PROTECTIO
N TEST
UNIT
EXTERNAL CONTROL BUS
CONTROL LINES
32 BIT
AB
32 BIT DB
PHYSICAL ADDRESS BUS
CODE FETCH / PAGE TABLE FETCH
INTERNAL CB
EFFECTIVE
AB
69. 80386
• 80386 SX – 100 PIN CHIP
24 BIT AB, VIRTUAL MODE SAME AS DX
16 BIT DATA BUS, FETCHES 2 BYTES AT
A TIME
• 80386 DX – 132 PIN CHIP
TRULY 32 BIT PROCESSOR
FETCHES 4 BYTES AT A TIME
70. 80386
• FEATURES:
32 BIT EXTENSION OF 80286 ARCHITECTURE
32 BIT REGISTERS AND DATA PATH
UPTO 4 GB OF PHYSICAL ADDRESS SPACE
UPTO 246
(64 TB) OF VIRTUAL MEMORY
32 BIT DB WITH A THROUGHPUT OF 32 MB/SEC USING 16
MHz CLOCK
71. 80386
• FEATURES:
MORE INSTRUCTION PIPELINING
MORE ON-CHIP MEM MANAGEMENT FACILITY
ON-CHIP ADDRESS TRANSLATION CACHE
4 BREAKPT REGISTERS AND OTHER SELF-TEST FEATURES
HIGHER CLOCK SPEED
72. 80386
• FEATURES:
OBJECT CODE COMPATIBLE WITH 8086 FAMILY
EXISTING 8086 APPLICATIONS CAN RUN IN PROTECTED
MODE (SEG SIZE IS 64K)
IN REAL MODE, 32 BIT EXTENSIONS MAY BE USED FOR
HIGHER SPEED OPERATIONS.
MEM MANAGER SUPPORTS SEGMENTATION – LARGE
BLOCK OF MAIN MEMORY IS ALLOCATED FOR INDIVIDUAL
PROGRAMS – MAX SEG SIZE IS NOT EQUAL TO 64K BUT 4 GB
73. 80386
• FEATURES:
PAGE ADDRESSING IS ALSO SUPPORTED WITH A FIXED
PAGE SIZE OF 4 KB
A PAGING CACHE STORES THE LAST 32 ENTRIES AND AT 4
KB PER PAGE ENTRY, 128 KB OF MEMORY CAN BE
DIRECTLY ADDRESSED
FLAGS: RF AND VM. RESUME FLAG IS USED DURING DEBUG
OPERATION. VM 8086 FLAG IS USED TO SELECT VM.
ALLOWS RUNNING OF 8086 SW IN A PROTECTED AND
PAGED SYSTEM
74. 80386
• FLAGS:
o VM – IF SET, WHILE 80386 IS IN PM, SWITCHES TO VIRTUAL
8086 OPERATION, HANDLING SEGMENT LOADS AS 8086 BUT
GENERATES EXCEPTION 13 FAULT ON PRIVILEDGED
OPCODES
o RF – THIS FLAG IS USED WITH THE DEBUG REG BREAKPTS.
IT IS CHECKED AT INST BOUNDARIES BEFORE BREAKPT
PROCESSING. WHEN RF IS SET, IT CAUSES ANY DEBUG
FAULT TO BE IGNORED ON THE NEXT INST. RF IS THEN
AUTOMATICALLY RESET AT THE SUCCESSFUL COMPLETION
OF EVERY INSTRUCTION
75. 80386
• FLAGS:
NT – IT APPLIES TO PROTECTED MODE. IT IS SET TO
INDICATE THAT THE EXECUTION OF THIS TASK IS NESTED
WITHIN ANOTHER TASK. IF SET, IT INDICATES THAT THE
CURRENT NESTED TASK’S TSS HAS A VALID BACK LINK TO
THE PREVIOUS TASK’S TSS. THIS BIT IS SET OR RESET BY
CONTROL TRANSFERS TO OTHER TASKS.
IOPL – THIS 2 BIT FIELD APPLIES TO PROTECTED MODE. IT
INDICATES THE NUMERICALLY MAXIMUM CURRENT
PRIVILEGE LEVEL VALUE PERMITTED TO EXECUTE I/O INSTS
WITHOUT GENERATING AN EXCEPTION 13 FAULT OR
CONSULTING THE I/O PERMISSION BITMAP.
76. 80386DX
• FUNCTIONAL PIN DIAGRAM:
CLK2
D0-D31
HOLD
HLDA
INTR
NMI
RESET
PEREQ
BUSY’
ERROR’
PROCESSO
R STATUS
&
CONTROL
LINES
COPROCESS
OR CONTROL
LINES
VCC
GND
A2-A31
BE0’ – BE3’
ADS’
W/R’
D/C’
M/IO’
LOCK’
NA’
BS16’
READY’
ADDRESS BUS
BUS CYCLE
DEFINITION
BUS CYCLE
CONTROL
INDICATES WHICH DB
BYTES ARE RELEVANT IN
CURRENT TRANSFER
TO ENABLE/DISABLE
PIPELINING
TRANSFERS ON ONLY
LOWER 16 BIT DB WHEN
ASSERTED
DYNAMIC BUS SIZING
77. 80386
• REGISTER ARCHITECTURE:
31 15 0
AH AL
BH BL
CH CL
DH DL
SI
DI
BP
SP
IP
FLAGS
EAX
EBX
ECX
EDX
ESI
EDI
EBP
ESP
EIP
EFLAGS
GENERAL REGISTERS
79. 80386
• REGISTER ARCHITECTURE:
15 0 63
0
SEGMENT
REGISTER
SEG. DESCRIPTOR REGISTERS
SELECTOR BASE ADDRESS, LIMIT, ETC.
CS
SS
DS
ES
FS
GS
80. 80386
• REGISTER ARCHITECTURE:
47 15
0
63
BASE ADD. LIMIT
SELECTOR
GDTR
IDTR
LDTR
TR
SYSTEM ADDRESS REGISTERS
GDT AND IDT ARE GLOBAL
SEGMENTS- 32 BIT LINEAR
ADDRESS AND 16 BIT LIMIT
VALUE.
LDTR AND TSSR ALSO
HOLD THE 16 BIT
SELECTOR. THESE ARE
TASK SPECIFIC SEGMENTS.
82. 80386
• REGISTER ARCHITECTURE:
LINEAR BP ADDRESS 0
LINEAR BP ADDRESS 1
LINEAR BP ADDRESS 2
LINEAR BP ADDRESS 3
RESERVED
RESERVED
DEBUG STATUS
DEBUG CONTROL
DEBUG REGISTERS
DR0
DR7
31 0
31 0
TEST CONTROL
TEST STATUS
TEST REGISTERS(FOR
PAGE CACHE)
83. 80386
• CR0 CONTAINS THE MSW – MONITOR COPROCESSOR,
PROTECTION ENABLE, EMULATE COPROCESSOR, TASK
SWITCH AND PAGING ENABLE
• CR2 HOLDS THE LINEAR ADDRESS THAT CAUSED THE LAST
PAGE FAULT DETECTED. THE ERROR CODE, PUSHED ON TO
THE PAGE FAULT HANDLER’S STACK WHEN IT IS INVOKED
PROVIDES ADDITIONAL STATUS INFORMATION ON THIS
PAGE FAULT.
• CR3 CONTAINS THE PHYSICAL BASE ADDRESS OF THE
PAGE DIRECTORY TABLE. PDT IS ALWAYS PAGE ALIGNED
(4KB ALIGNED)
84. 80386
• ADDRESS TRANSLATION: LOGICAL, LINEAR, PHYSICAL
INDEX
BASE DISPLACEMENT
1, 2, 4, 8
SEGMENT
REGS.
DESCRIPT
OR REGS.
SEGMENTATI
ON UNIT
PAGING
UNIT
PHYSICAL
MEMORYLOGICAL/VIRTUAL
LINEAR
PHYSICAL
DESCRI
PTOR
INDEX
85. 80386
• CR0:
PG : IF SET, ENABLES ON-CHIP PAGING UNIT
ET: PROC. EXTN.TYPE – IF SET, 80387 COMPATIBLE 32 BIT
PROTOCOL IS USED. IF RESET, 80287 COMPATIBLE 16 BIT
PROTOCOL IS USED.
TS : TASK SWITCH – IT IS AUTOMATICALLY SET WHENEVER
ANY TASK SWITCH OPERATION IS PERFORMED. IF SET, A
COPROCESSOR ESCAPE CODE WILL CAUSE A COPROC. NOT
AVAILABLE TRAP.
86. 80386
• CR0:
EM : EMULATE COPROC. – IT IS SET TO CAUSE ALL COPROC.
OPCODES TO GENERATE A COPROC NOT AV FAULT. IT IS RESET TO
ALLOW COPROC. OPCODES TO BE EXECUTED ON 80287/80387
MP : MONITOR COPROC. – IT IS USED WITH TS BIT TO DETERMINE IF
THE WAIT OPCODE WILL GENERATE A COPROC NOT AV FAULT
WHEN TS=1
WHEN MP=1, TS=1, THE WAIT OPCODE GENERATES A TRAP ELSE
NOT.
PE : PROT. ENABLE – IT IS SET TO ENABLE THE PROTECTED MODE.
87. 80386
• TLB:
ASSOCIATED ON-CHIP CACHE
TO ENSURE HIGH VIRTUAL MEMORY PERFORMANCE
IT CONTAINS THE MAPPING INFO FOR THE 32 MOST
RECENTLY USED PAGES.
IT ENABLES 386 TO TRANSLATE MOST ADDRESSES ON CHIP
WITHOUT CONSULTING A MEM BASED PAGE TABLE.
TYPICALLY, 98-99% ADDRESS REFERENCES HIT A TLB
ENTRY.
88. 80386
• COMPLETE 32 BIT ARCHITECTURE
• CONFIGURABLE PROTECTION – FROM ZERO TO FOUR
PRIVILEGE LEVELS
• IMPLEMENTED IN CHMOS III, A SEMICONDUCTOR PROCESS
THAT COMBINES THE HIGH FREQ OF HMOS WITH THE
MODEST POWER REQUIREMENTS OF CMOS
• INTERNALLY, IT IS PARTITIONED INTO SIX UNITS THAT
OPERATE IN PARALLEL, SYNCHRONIZING AS NECESSARY.
89. 80386
• BY PIPELINING ITS FUNCTIONAL UNITS, IT CAN OVERLAP
THE EXECUTION OF DIFFERENT STAGES OF ONE INST AND
CAN PROCESS MULTIPLE INSTS SIMULTANEOUSLY
• ITS MULT/DIVIDE UNIT CAN PERFORM 32-BIT
MULTIPLICATION IN 9-41 CLOCK CYCLES, DEPENDING UPON
THE NO OF SIGNIFICANT DIGITS. IT CAN DIVIDE 32 BIT
OPERANDS IN 38 CLOCKS (UNSIGNED) 0R 43 CLOCKS
(SIGNED)
• ITS BARREL SHIFTER CAN SHIFT 1-64 BITS IN A SINGLE
CLOCK CYCLE.
90. 80386
• ADDRESSING MODES:11 MODES FOR INSTRUCTIONS TO
SPECIFY OPERANDS
• THE MODES ARE OPTIMIZED TO ALLOW THE EFFICIENT
EXECUTION OF HIGH LEVEL LANGUAGES.
• 2 MODES PROVIDE FOR INSTS THAT OPERATE ON
REGISTER OR IMMEDIATE OPERANDS.
1. REGISTER : THE OPERAND IS LOCATED IN ONE OF THE
REGISTERS.
2. IMMEDIATE : THE OPERAND IS INCLUDED IN THE INST AS
PART OF THE OPCODE.
91. 80386
• THE REMAINING 9 ARE MEMORY ADDRESSING MODES. IT
PROVIDES A MECHANISM FOR SPECIFYING THE EFFECTIVE
ADDRESS OF AN OPERAND.
• THE LINEAR ADDRESS CONSISTS OF 2 COMPONENTS –
SEGMENT BASE ADDRESS AND EFFECTIVE ADDRESS.
• THE EFFECTIVE ADDRESS IS CALCULATED BY USING
COMBINATIONS OF THE FOLLOWING FOUR ADDRESS
ELEMENTS: DISPLACEMENT, BASE, INDEX AND SCALE.
92. 80386
• DISPLACEMENT IS AN 8 OR 32 BIT IMMEDIATE VALUE FOLLOWING
THE INST.
• BASE IS THE CONTENT OF ANY GPR.
• INDEX IS THE CONTENT OF ANT GPR EXCEPT FOR ESP
• SCALE – FOR MULTIPLYING THE INDEX REG VALUE BY THE SCALE
FACTOR.
• COMBINATION OFTHESE 4 COMPONENTS MAKE UP THE 9
ADDITIONAL ADDRESSING MODES.
• THERE IS NO PERFORMANCE DEGRADATION SINCE THE EFFECTIVE
ADDRESS CALCULATION IS PIPELINED WITH THE EXECUTION OF
OTHER INSTRUCTIONS. THE EXCEPTION IS THE USE OF BASE AND
INDEX COMPONENTS WHERE AN ADDITIONAL CLOCK IS REQUIRED.
93. 80386
3. DIRECT : THE OPERAND’S OFFSET IS CONTAINED AS PART
OF THE INST AS AN 8, 16 OR 32 BIT DISPLACEMENT eg.,
INC WORD PTR [500]
4. INDIRECT : A BASE REGISTER CONTAINS THE ADDRESS
OF THE OPERAND MOV [ECX], EDX
5. BASED : BASE REG’S CONTENT IS ADDED TO
DISPLACEMENT TO FORM THE OPERAND’S OFFSET
eg.,MOV ECX,[EAX +24]
6. INDEXED : INDEX REG’S CONTENTS ARE ADDED TO DISP
TO FORM THE OPERAND’S OFFSET ADD EAX, TABLE[ESI]
94. 80386
7. SCALED INDEXED : INDEX REG’S CONTENT IS MULTIPLIED
BY A SCALING FACTOR WHICH IS ADDED TO DISP TO
FORM THE OPERAND’S OFFSET IMUL EBX, TABLE[ESI*4],7
8. BASED INDEXED : BASE REG CONTENTS ARE ADDED TO
INDEX REG TO FORM THE EFFECTIVE ADDRESS OF THE
OPERAND MOV EAX, [ESI][EBX]
9. BASED SCALED INDEXED : INDEX REG CONTENT IS
MULTIPLIED BY A SCALING FACTOR AND THE RESULT IS
ADDED TO THE CONTENTS OF A BASE REG TO OBTAIN
THE OPERAND’S OFFSET MOV ECX, [EDX*8][EAX]
95. 80386
10. BASED INDEXED WITH DISP:
THE CONTENTS OF AN INDEX REG AND A BASE REG AND
A DISPLACEMENT ARE ALL SUMMED TOGETHER TO FORM
THE OPERAND OFFSET. ADD EDX,[ESI][EBP+00FFFFF0H]
11. BASED SCALED INDEXED WITH DISP:
THE CONTENTS OF INDEX REG ARE MULTIPLIED BY A
SCALING FACTOR, THE RESULT IS ADDED TO THE
CONTENTS OF A BASE REG AND A DISP TO FORM THE
OPERAND’S OFFSET
eg., MOV EAX, LOCALTABLE [EDI*4][EBP+80]
97. 80486
• SAME REGISTER ARCHITECTURE AS 80386
• SAME SEGMENT REGISTERS
• THE IP ADDRESSES THE PROG LOCATED WITHIN 1 MB OF
MEMORY IN COMBINATION WITH CS OR EIP TO ADDRESS A
PROGRAM AT ANY LOCATION WITHIN THE 4 GB MEMORY
SYSTEM.
• IN PROTECTED MODE OPERATION, THE SEGMENT
REGISTERS FUNCTION TO HOLD SELECTORS AS IT DID IN
80386
98. 80486
• IT ALSO CONTAINS THE GLOBAL, LOCAL AND IDT REGS AND
MMU AS IN 80386
• EFLAG REG CONTAINS AN ADDITIONAL BIT – AC
[ALIGNMENT CHECK]
• IT IS USED TO INDICATE THAT THE PROCESSOR HAS
ACCESSED A WORD AT AN ODD ADDRESS OR A DOUBLE
WORD STORED AT A NON-DOUBLEWORD BOUNDARY.
• EFFICIENT SW EXECUTION REQUIRES THAT THE DATA BE
STORED AT WORD OR DOUBLEWORD BOUNDARIES.
99. 80486
• LIKE 80386, IT CAN ADDRESS 4 GB MEMORY. IT HAS AN
ADDITIONAL 8KB CACHE.
• ANOTHER ADDITION IS PARITY GEN/CHECKER. IT IS USED TO
DETERMINE WHETHER THE DATA HAS BEEN CORRECTLY
READ FROM A MEMORY LOCATION OR NOT.
• EVEN PARITY IS GENERATED DURING EACH WRITE CYCLE
AND A PARITY BIT IS PROVIDED FOR EACH BYTE OF
MEMORY.
• THE PARITY CHECK BITS APPEAR ON PINS, WHICH ARE
PARITY INPUTS AS WELL AS OUTPUTS.
100. 80486
• THESE ARE STORED IN MEMORY DURING EACH WRITE
CYCLE AND READ FROM MEMORY DURING EACH READ
CYCLE.
• ON READ, THE PROCESSOR CHECKS PARITY AND
GENERATES A PARITY CHECK ERROR, IF IT OCCURS, ON A
PIN PCHK’.
• A PARITY ERROR CAUSES NO CHANGE IN PROCESSING
UNLESS THE USER APPLIES THE SIGNAL PCHK’ TO AN
INTERRUPT INPUT.
101. 80486
• CACHE HAS BEEN ORGANIZED AS A 4-WAY SET
ASSOCIATIVE CACHE WITH EACH LINE CONTAINING 16
BYTES OR 4 DOUBLEWORDS OF DATA.
• THE CACHE OPERATES AS A WRITE-THROUGH CACHE. THE
CACHE CHANGES ONLY WHEN A MISS OCCURS ie., THE
DATA WRITTEN TO A MEMORY LOCATION NOT ALREADY
STORED ARE NOT WRITTEN TO THE CACHE.
• IN MANY CASES, MOST OF THE ACTIVE PORTION OF A
PROGRAM IS FOUND INSIDE THE CACHE MEMORY. THIS
CAUSES THE EXECUTION TO OCCUR AT THE RATE OF 1
CLOCK CYCLE FOR MANY OF THE INSTS COMMONLY USED
IN A PROGRAM.
102. 80486
• DATA CAN ALSO BE STORED IN THE CACHE, BUT ITS
IMPACT ON THE EXECUTION SPEED IS LESS AS DATA ARE
NOT REFERENCED REPEATEDLY AS ARE MANY PORTIONS
OF THE PROGRAM.
• FOR THE CACHE, 2 ADDITIONAL BITS ARE THERE IN CR0 –
CD AND NW (CACHE DISABLE AND NON-CACHE WRITE
THROUGH)
• IF CD=1 ARE CACHE OPERATIONS ARE INHIBITED.
• THE NW BIT IS USED TO INHIBIT CACHE WRITE THROUGH
OPERATION. AS WITH CD, CACHE WRITE THROUGH IS
INHIBITED ONLY FOR TESTING AND NORMALLY IT IS CLEAR.
103. 80486
• THE CACHE IS FILLED USING THE BURST CYCLES.
• WHEN A BUS LINE IS FILLED, IT MUST ACQUIRE 4, 32 BIT
NOS. FROM THE MEMORY TO FILL A LINE IN THE CACHE.
FILLING IS DONE WITH A BURST CYCLE. THE BURST CYCLE
IS A SPECIAL MEMORY WHERE 4, 32 BIT NOS ARE FETCHED
FROM THE MEMORY SYSTEM IN 5 CLOCKING PERIODS
ASSUMING THAT THE SPEED OF THE MEMORY IS
SUFFICIENT AND NO WAIT STATES ARE REQUIRED.
• MEMORY MANAGEMENT IS SAME. THE ONLY DIFF IS THAT
80486 PAGING SYSTEM CAN DISABLE CACHING FOR
SECTIONS OF TRANSLATED MEM PAGES WHILE 80386
COULD NOT. FOR THIS NEW CONTROL BITS ARE ADDED –
PWT & PCD.
104. 80486
• PWT CONTROLS HOW THE CACHE FUNCTIONS FOR A WRITE
OPERATION OF THE EXT CACHE MEMORY. IT DOESNOT
CONTROL WRITING TO THE INTERNAL CACHE.
• EXTERNALLY, IT CAN BE USED TO DICTATE THE WRITE
THROUGH POLICY OF THE EXTERNAL CACHE.
• PCD BIT CONTROLS THE ON-CHIP CACHE. IF PCD=0, THE ON-
CHIP CACHE IS ENABLED FOR THE CURRENT PAGE OF THE
MEMORY
• BECAUSE OF THE CACHE MEM, IT HAS CACHE TEST REGS
ON CHIP – TR3 FOR CACHE DATA; TR4 FOR CACHE STATUS
AND TR5 FOR CACHE CONTROL.
105. 80486
• NEW INSTS TO CONTROL THE INTERNAL CACHE ARE:
• XADD – TO ALLOW ADDITION
• CMPXCHG – COMPARISON WITH AN EXCHANGE
• BSWAP – BYTE SWAP
• IT HAS A BUILT-IN SELF-TEST (BIST) THAT TESTS THE
MICROPROCESSOR, COPROCESSOR AND CACHE WHEN THE
CHIP IS RESET. IF IT PASSES THE TEST, EAX =0
106. PENTIUM
• EQUIVALENT TO TWO 80486 CPUs
• 64 BIT DB, 32 BIT AB, 60-200 MHz (P1)
• PGA
• SUPERSCALAR ARCHITECTURE
• 16 KB L1 CACHE
• MORE SOPHISTICATED INST PIPELINING
• 3.3V
107. PENTIUM
• SUPERSCALAR ALLOWS MULTIPLE INSTS TO EXECUTE IN
PARALLEL.
• WITH THE ADVANCEMENT OF TECHNOLOGY, CIRCUITS
BECAME MORE COMPLEX BUT THE ADVANTAGE WAS THAT
SOME MORE ROOM WITH TIME BECAME AVAILABLE ON THE
SAME SIZE CHIP, WHICH THE DESIGNER’S TRIED TO USE
FOR THE IMPROVEMENT IN THE EXECUTION OF INSTS
THEREBY ENHANCING THE PERFORMANCE OF THE
PROCESSOR.
• THE RESULT WAS INCORPORATION OF ON-CHIP CACHE AND
IMPROVEMENT IN INST PIPELINING.
108. PENTIUM
• THE LATEST STEP IN THIS EVOLUTIONARY PROCESS IS THE
DEVOPMENT OF SUPERSCALAR PROCESSORS.
• IT MEANS THAT THESE PROCS ARE SCALAR PROCS THAT
ARE CAPABLE OF EXECUTING MORE THAN ONE INST IN
EACH CYCLE.
• IT IS MADE POSSIBLE BY (1) USING AN INST FETCH UNIT
THAT CAN FETCH MORE THAN ONE INST AT A TIME FROM
CACHE (2) INST DECODING LOGIC THAT CAN DECIDE WHEN
INSTS ARE INDEPENDENT AND THUS EXECUTED
SIMULTANEOUSLY AND (3) USING SUFFICIENT EXECUTION
UNITS TO BE ABLE TO PROCESS SEVERAL INSTS AT A TIME.
109. PENTIUM
• THESE EUs MAY BE PIPELINED. THE SUPERSCALAR
DESIGNS USE INST LEVEL PARALLELISM FOR IMPROVED
IMPLEMENTATION OF THE EARLIER SCALAR DESIGNS.
• SUPERSCALAR ARCHITECTURE HAS AN INST LEVEL
PARALLEL ARCHITECTURE WHICH EMPLOYS REPLICATION.
• THE EXECUTION UNITS ARE REPLICATED SO THAT THEY
CAN EXECUTE SAME OPERATION SIMULTANEOUSLY ON
MANY DATA ELEMENTS BECAUSE THE REPLICATED
RESOURCES ARE AVAILABLE.
111. PENTIUM
• THE BASIC STRUCTURE CONSISTS A NO OF EUs, EACH
CAPABLE OF PARALLEL OPERATION ON DATA FETCHED
FROM A REG FILE.
• IT ACCEPTS A SEQUENTIAL STREAM OF INSTS BUT CAN
ISSUE MORE THAN ONE INST TO THE EU IN EACH CYCLE.
• MULTIPLE EUs EXECUTE INSTS AND WRITE BACK RESULTS
INTO THE REG FILE SIMULTANEOUSLY.
• THE SUPERSCALAR ARCHITECTURE REQUIRES HIGHLY
MULTI-PORTED REG FILES SO THAT ONE OUTPUT PORT AND
2-3 INPUT PORTS COULD BE ASSIGNED TO EACH EU.
112. PENTIUM
• THE CONCEPT OF PIPELINING IN SUPERSCALAR PROC
DIFFERS FROM OTHER PIPELINED PROCS IN THE SENSE
THAT OTHER PIPELINED PROCS WORK LIKE AN ASSEMBLY
LINE WHEREAS SUPERSCALAR ARCH HAVE A NO OF
CONCURRENTLY WORKING EUs WHERE EACH EXECUTION
UNIT HAS A SPECIFIC NO OF PIPELINE STAGES DEPENDING
UPON THE KIND OF TASK TO BE PERFORMED.
• THE EU PIPELINE, IN GENERAL, CAN HAVE 2 TO 10 STAGES.
THE SUPERSCALAR PROC RECEIVES A SEQUENTIAL
STREAM OF INSTS.
• THE DECODE AND ISSUE UNIT THEN ISSUES MULTIPLE
INSTS FOR THE MULTIPLE EUs IN EACH CYCLE.
113. PENTIUM
• THE WORKING OF PIPELINING IN SUPERSCALAR PROC
MAY BE DIVIDED AS
1. PARALLEL DECODING
2. SUPERSCALAR INST ISSUE
3. PARALLEL INST EXECUTION
4. PRESERVING SEQUENTIAL CONSISTENCY OF EXECUTION
5. PRESERVING SEQUENTIAL CONSISTENCY OF EXCEPTION
PROCESSING
114. PENTIUM
• THE SUPERSCALAR PROCS HAVE TO ISSUE MULTIPLE INSTS
PER CYCLE, SO THE FIRST TASK IS PARALLEL DECODING.
• THE PROC DECODES SEVERAL INSTS IN A SINGLE CLOCK
CYCLE.
• IT CHECKS FOR DEPENDENCIES AMONG INSTS DURING
DECODING FROM TWO PERSPECTIVES:
WHETHER THE INSTS TO BE ISSUED DEPEND ON THE INSTS
CURRENTLY IN EXECUTION AND
WHETHER THERE ARE DEPENDENCIES AMONG THE INSTS
WHICH ARE CANDIDATES FOR THE NEXT ISSUE.
115. PENTIUM
• THE NEXT STEP IS INST ISSUE. IT DEALS WITH TWO
ASPECTS:
HOW DEPENDENCIES ARE HANDLED DURING THE ISSUE
PROCESS AND
WHAT IS THE MAXIMUM NO OF INSTS A SUPERSCALAR
PROC CAN ISSUE IN EACH CYCLE.
• THE THIRD STEP IS PARALLEL EXECUTION OF INSTS.
116. PENTIUM
• WHEN INSTS ARE EXECUTED IN PARALLEL, IT WILL
GENERALLY FINISH IN OUT-OF-PROGRAM ORDER.
• UNEQUAL EXECUTION TIME FORCES INST TO FINISH OUT-
OF-ORDER, EVEN THOUGH THEY HAVE BEEN ISSUED IN
ORDER.
• TO AVOID THIS OUT-OF-ORDER FINISHING OF INSTS IN
SUPERSCALAR ARCHITECTURE BECAUSE OF MULTIPLE
EUs, THE INSTS SHOULD BE ISSUED IN ORDER AND ALL EUs
OPERATING IN PARALLEL MUST HAVE EQUAL EXECUTION
TIME.
117. PENTIUM
• THESE CONDITIONS MAY BE FULFILLED BY USING A DUAL
PIPELINE AND LOCK-STEPPING THEM ie., LENGTHENING THE
SHORTER PIPELINES BY INTRODUCING UNUSED EXTRA
CYCLES INTO IT.
• NEXT PHASE IS THE PRESERVATION OF THE SEQUENTIAL
CONSISTENCY OF INST EXECUTION. THIS IS DONE BY
DECOUPLING THE GENERATION OF RESULTS FROM
WRITING THEM BACK INTO THE SPECIFIED REG OR MEM
LOCATION.
• WHILE THE RESULTS ARE GENERATED IN PARALLEL BY THE
EUs, THE PROGRAM STATE IS UPDATED IN A DECOUPLED
MANNER SEQUENTIALLY IN THE PROGRAM ORDER.
118. PENTIUM
• THE FINAL STEP IS THE PRESERVATION OF THE
SEQUENTIAL CONSISTENCY OF EXCEPTION PROCESSING.
WHEN INSTS ARE EXECUTED IN PARALLEL, INTERRUPT
REQUESTS WHICH ARE CAUSED BY EXCEPTIONS ARISING IN
INST EXECUTION, ARE ALSO GENERATED OUT-OF-ORDER.
• SO, STRONG SEQUENTIAL CONSISTENCY WITH REGARD TO
EXCEPTION PROCESSING SO THAT AFTER INTERRUPTS THE
STATE OF THE PROC REMAINS CONSISTENT, IS ACHIEVED
BY IN ORDER INST COMPLETION.
119. PENTIUM
• SO, IN SUPERSCALAR PROCS MULTIPLE PIPELINES
OPERATE IN PARALLEL.
• A n DEGREE SUPERSCALAR PROC HAS n PIPELINES.
• IF EACH PIPELINE HAS K STAGES, POTENTIAL SPEEDUP
OVER A SUPERSCALAR IMPLEMENTATION IS K.n
• IN PRACTICE, IT IS DIFFICULT TO KEEP MULTIPLE PIPELINES
BUSY, SO MANY IMPLEMENTATIONS HAVE BEEN LIMITED TO
THE DEGREE OF 2 OR 3.
