1. Programmable Interval timer 8253 / 8254

2. WHY 8253???

3. 8253 VS 8254

4. 8254 BLOCK

5. BLOCK DIAGRAM OF 8254

8. 8254 PIN DIAGRAM

9. CONTROL WORD FORMAT

12. The output becomes a logic 0 when the control word is written

13. Remains low even after count value loaded in counter

14. Counter starts decrementing after falling edge of clock

15. The OUT goes high upon reaching the terminal count & remains high till reloading

16. OUT can be used as interrupt

17. Writing a count register , when previous counting is in process  first byte when loaded stops the previous count,  second byte when loaded starts new count

18. Gate high  normal counting

21. gate input is used as trigger input

22. output remains high till the count is loaded

23. After application of trigger, output goes low and remains low till count becomes zero

24. Another count loaded, when output already low it does not disturb counting until a new trigger is applied at the gate

27. When N is loaded as count  after N pulses  OUT goes low for only one clock cycle then, count N is reloaded  OUT becomes high for N clock pulses

28. The number of clock pulses between the two low pulses is equal to the count loaded

29. gate  logic 0  no counting

31. When count N loaded is odd  output remains HIGH for (N+1)/2 and low for (N-1)/2.

32. Repeated operation gives square wave

33. Generates a continuous square-wave with G set to 1.

36. When count is loaded counting down starts

37. On reaching terminal count output goes low for only one clock cycle, and then again output goes HIGH

38. The above said low pulse can be used as a strobe for interfacing MP with peripherals

39. When GATE is LOW  counting is inhibited and count is latched

42. Mode is used to generate a delayed strobe in response to an externally generated signal

43. Once mode is programmed and counter loaded, OUT goes HIGH

44. Counter starts counting after the rising edge of the trigger (GATE)

45. The OUTPUT goes LOW for one clock period, when the terminal count is reached

46. Output will not go LOW until the counter content becomes zero after the rising edge of any trigger

50. the Counter Latch Command

53. two other bits, D5 and D4, distinguish this command from a Control Word

54. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch Command is ignored.

57. check the counter is in NULL state (0) or not

58. how the counter is programmed