My final project for CSCI E-93 Computer Architecture course called SAM (Shahrul Accumulator Machine). The propose architecture is a single accumulator machine and which was designed based on below requirements: 1. The computer should be able to address 64kb memory 2. The computer should be able to read/write variable length strings from virtual terminal 3. The computer should be to convert from two bytes (henceforth referred to as a word) in two's-complement notation in memory into a string of ASCII characters representing that word's decimal value and vice versa. 4. The computer must be able to multiply two two's-complement words to produce at least a single two's-complement word product. 5. The computer must be able to prompt the user to enter two integers, accept those two integers, multiply them together, and print out the product.

1. HARVARD UNIVERSITY EXTENSION
E-93: Computer Architecture
Final Project
Shahrul Accumulator Machine (SAM)
By: Sharudin, Mohd Shahrul Zharif
19/12/14
This document contains the Final Project documentation of E-93 Computer Architecture Course for
Fall, 2014.

2. HU Extension Final Project E-93 Computer Architecture
Contents
Introduction..........................................................................................................................................3
Brief Description..................................................................................................................................4
SAM Block Diagram............................................................................................................................7
Memory Access....................................................................................................................................9
Unconditional Branching......................................................................................................................9
Conditional Branching .........................................................................................................................9
Procedure Call......................................................................................................................................9
Arithmetic & Logical Operations.......................................................................................................10
SAM Arithmetic Logic Unit...............................................................................................................11
Memory..............................................................................................................................................12
I/O Interfacing....................................................................................................................................12
Special Features: Hardware Multiplier...............................................................................................14
Instruction Set.....................................................................................................................................15
Assembly Language...........................................................................................................................17
Empty Lines..............................................................................................................................17
Comment Lines.........................................................................................................................17
Instruction Lines.......................................................................................................................17
Label Definition Lines..............................................................................................................18
Directives..................................................................................................................................18
Code Snapshot...........................................................................................................................19
Important notes in developing assembly code for SAM...........................................................20
SAM Assembler..................................................................................................................................21
Building the assembler..............................................................................................................21
System Requirement........................................................................................................21
Assembling the code into MIF file..................................................................................21
SAM Emulator....................................................................................................................................22
System Requirement.................................................................................................................22
Building the emulator................................................................................................................22
Running the emulator................................................................................................................22
Emulator Screenshot.................................................................................................................23
DE2-115 LEDs, Buttons, Switches mapping.....................................................................................24
Appendix............................................................................................................................................25
SAM Architecture.....................................................................................................................25
SAM ALU.................................................................................................................................25
SAM Hardware Multiplier........................................................................................................25
SAM FSM.................................................................................................................................25
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3. HU Extension Final Project E-93 Computer Architecture
Introduction
The block diagram below is the CPU design of my final project for CSCI E-93 Computer
Architecture course called SAM (Shahrul Accumulator Machine). The propose architecture is a
single accumulator machine and which was designed based on below requirements:
1. The computer should be able to address 64kb memory
2. The computer should be able to read/write variable length strings from virtual terminal
3. The computer should be to convert from two bytes (henceforth referred to as a word) in
two's-complement notation in memory into a string of ASCII characters representing that
word's decimal value and vice versa.
4. The computer must be able to multiply two two's-complement words to produce at least a
single two's-complement word product.
5. The computer must be able to prompt the user to enter two integers, accept those two
integers, multiply them together, and print out the product.
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4. Brief Description
The basic word size of the proposed computer is 2 bytes (a word). All its registers are16-bit in size.
Mnemonic Register Description
ACC Accumulator General purpose register used to hold the intermediate
storage for arithmetic, and memory operations.
PC Program Counter Hold the address of the next instruction to be executed.
PC is considered a special register and cannot be used
as General Purpose Register. Value of PC can only be
modified by procedure call, branch, and return
statements. PC value is increase by 2 at EXECUTE
state.
IR Instruction Register Holds the current instruction being executed. IR is not
accessible by user.
MAR Memory Address Register Holds the memory location of data that needs to be
accessed. It can either store the address of an
instruction, or data. This register is not visible to
programmer.
MDR Memory Data Register Holds data to be stored in memory or the data after
being retrieved from memory.
ZERO Zero Register 1-bit register which holds value 1 if the result from
ALU operation is 0 or 0 if the result is non-zero.
AR Address Register Special register which can access all 64kb memory
address for branching, procedure call, and memory
operations (load and store). It also can be used as
counter.
When use in procedure call (CALL), AR will store the
address of the next instruction (the one immediately
after the jump) from PC register and load it back into
PC register at the end of procedure (RETURN).
AR can also be used to branch to other program
location which is outside the 211
memory address
supported by normal GOTO statement. The command
to branch to instructions location defined in AR register
is GOTOAR.
If memory operations need to access memory area
outside of 211
memory address, AR register can be used
to point to the memory address. LOADAR is used to
load the value from memory address defined in AR
register and STORAR is used to store value in
accumulator into memory address defined in AR
register.
AR register can also be used as a counter up or down.
Value of AR can be loaded from accumulator using
MOVAR instruction. On the other hand, MOVAC will

5. HU Extension Problem Set 2 (4th
revision) E-93 Computer Architecture
load the value of AR into accumulator. INC x
instruction will increase the value of AR by x, and
DEC x will decrease AR by x. x can be any integer
from 0 to 2046.
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6. HU Extension Problem Set 2 (4th
revision) E-93 Computer Architecture
Sharudin, Mohd Shahrul Zharif Page 6

7. HU Extension Final Project E-93 Computer Architecture
SAM Block Diagram
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8. HU Extension Final Project E-93 Computer Architecture
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9. HU Extension Final Project
E-93 Computer Architecture
Memory Access
Access to memory is performed through normal Load and Store instructions. Load instruction will
fetch data from memory and place it inside the accumulator, whereas Store instruction will store the
accumulator content into the memory.
LOAD 0x7ff # this will fetch data from memory address 0xff and place it into
accumulator
STOR 0x7ff # this will fetch data from accumulator and place it into memory
address 0xff
LOAD and STOR instructions can only access up to 211
memory addresses. If further memory
address needs to be access, AR register can be used by manipulating the address in accumulator
before loading it into AR:
#load 0x7ff value into accumulator. This is the maximum value addressable by LOAD
command
LOADA 0x7ff
#Add 1 to 0x7ff
ADDA 0x01
#Load the accumulator value into AR. AR = 0x800
MOVAR
#Fetch the value from memory address loaded in AR into accumulator
LOADAR
#Acc=memory[AR]:
Unconditional Branching
SAM support unconditional branching using GOTO and GOTOAR instructions. GOTO instruction
will cause SAM to execute the next instruction from memory location specified in the operand,
whereas GOTOAR instruction will execute the next instruction from memory location defined in
Address Register.
Conditional Branching
The design implements only one conditional instruction, If-Zero-Goto (IFZGOTO). This instruction
will cause the computer to execute instructions at a different location if the result of last arithmetic
operation (excluding multiplication) is zero.
Procedure Call
Procedure call is possible in this design through the availability of CALL and RETURN instructions.
CALL will change the instruction execution to another instruction’s address while saving the
Program Counter value after the call into Address Register.
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10. HU Extension Final Project
E-93 Computer Architecture
RETURN instruction will load the Program counter with Address Register content which returns
back the program execution to the next instruction in the program after the CALL instruction.
Arithmetic & Logical Operations
SAM supports 3 arithmetics operations: addition, subtraction, set-less-than, and 5 logic operations:
And, Nand, shift-left-logical, shift-right-logical, shift-left-arithmetic.
Arithmetic and logical operations can be made between accumulator and an operand value ( ADDA,
SUBA, SLTA,ANDA, NANDA), or a value from memory (ADD, SUB,AND, NAND). Shift
operations are always performed on the value in accumulator.
It also has set-less-than (SLT) instruction which will set the accumulator content to 1 if the
accumulator value is less than the value it compared to.
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11. HU Extension Final Project E-93 Computer Architecture
SAM Arithmetic Logic Unit
The ALU will support 8 Arithmetic and Logic function and controlled by 7 bit control lines. It takes in two 16-bit input and produce a 16-bit result.
Below diagram describes the ALU design in details.
Full size of the ALU’s diagram:
ALU(v3).png
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12. HU Extension Final Project E-93 Computer Architecture
The ALU has a 1-bit register ZERO register, which will set to 1 when 16-bit result from ALU is 0,
and reset to 0 when the ALU result is non-zero. The table below describes the control line
configuration for each type of ALU’s function:
ALUOp Function ALU Control Lines ()
Binvert Cin0(LSB) ShiftType ShiftDirection SrcSel
000 And 0 0 X X 001
001 Nand 1 0 X X 010
010 Add 0 0 X X 000
011 Subtract 1 1 X X 000
100 Set-if-less-than 1 1 X X 100
101 Shift right
logical
X X 0 1 011
110 Shift right
arithmetic
X X 1 1 011
111 Shift left logical X X 0 0 011
This computer will include 3 shift instructions: Shift-Left-Logical (SLA), Shift-Right-Logical
(SRL), and Shift-Right-Arithmetic (SRA). These instructions do not have operands. Shift-Left-
Arithmetic (SLA) instruction will shift the bit to the left by 1-bit. In contrast, Shift-Right-Logical
and Shift-Right-Arithmetic will shift the bit to the right by 1 position. SRL will put zero into the
Most-Significant-Bit (MSB), whereas SRA will replicates the value of MSB to fill the empty bit
position.
Memory
Memory addresses will be available up to 32kb in RAM. The memory will accept 16 bit input as the
address and data. LOAD and STORE instructions can only address up to 2047 memory location. If
higher memory location needs to be access, AR register should be used together with LOADAR and
STORAR instructions.
I/O Interfacing
The machine will have an I/O interface that is character-based and memory-mapped. Three 16-bit
word-addressable memory addresses are used:
1) The input/output control register, REG_IOCONTROL,
2) The input/output character buffer #1, REG_IOBUFFER_1, and
3) The input/output character buffer #2, REG_IOBUFFER_2.
Address Name Description
0xFF00 REG_IOCONTROL Read/write control register
0xFF02 REG_IOBUFFER_1 Serial port device (RS-232) I/O buffer
0xFF04 REG_IOBUFFER_2 PS/2 port I/O buffer and LCD device
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13. HU Extension Final Project E-93 Computer Architecture
The table above describes the memory location of each I/O interface. REG_IOCONTROL registers
serves as the control register for both REG_IOBUFFER_1 and REG_IOBUFFER_2 registers.
Content of IOCONTROL can be read to check the status of devices mapped to REG_IOBUFFER_1
and REG_IOBUFFER_2, or written to clear the I/O buffer of the devices.
Bit Name (Read Bit/Write Bit) When bit read When bit write
0 BIT_SERIAL_INPUTREADY /
BIT_SERIAL_INPUTFLUSH
If set, there is a character
ready to be read from the
serial port device (RS-
232) via
REG_IOBUFFER_1
If set, flushes the serial
port (RS-232) input
queue.
1 BIT_SERIAL_OUTPUTREADY
/ BIT_SERIAL_OUTPUTFLUSH
If set, the serial port
device (RS-232) is ready
to accept a character by
writing that character to
REG_IOBUFFER_1.
After the character is
written to
REG_IOBUFFER_1, it
will be transmitted from
the Altera DE2-70 (or
DE2-115) via the serial
port.
If set, flushes the serial
port (RS-232) output
queue.
2 BIT_PS2_INPUTREADY /
BIT_PS2_INPUTFLUSH
If set, there is a character
ready to be read from the
PS/2 port device via
REG_IOBUFFER_2, i.e.,
the user has sent at least
one character to the
Altera DE2-70 (or DE2-
115) via the PS/2 port.
If set, flushes the PS/2
port input queue.
3 BIT_LCD_OUTPUTREADY /
BIT_LCD_OUTPUTFLUSH
If set, the LCD device is
ready to accept a
character by writing that
character to
REG_IOBUFFER_2.
After the character is
written to
REG_IOBUFFER_2, it
will be displayed on the
Altera DE2-70's (or DE2-
115's) LCD display.
If set, flushes the LCD
device output queue.
When REG_IOCONTROL register is read, the first 4 most significant bits if its contents will show
status of both REG_IOBUFFER_1 and REG_IOBUFFER_2 as defined in the table above. On the
other hand, write operation on REG_IOCONTROL register will flushes the input/output buffer of
REG_IOBUFFER_1 and REG_IOBUFFER_2 depending on which bit is set.
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14. HU Extension Final Project E-93 Computer Architecture
Special Features: Hardware Multiplier
The single accumulator machine will feature a hardware multiplier. The multiplier will take in two
16-bits input from and produce the multiplication result in one cycle. Since the multiplication
process is fast, the Multiplier module will always makes the result available even if not required.
The multiplier will be able to perform multiplication on two 2's complement word (16-bits) and
produce a single two's-complement word product. Since the Multiplier can only hold 16-bit result,
any multiplication which produces a value more than 216
will make the result invalid.
The design was based on 8-bit multiplier design described in a paper created by Muhammad Awan1
1
Awan, Muhammad. "PROJECT TITLE: An8-bit Multiplier Circuit. COURSE NUMBER & NAME: EE-211 Digital
Logic Design. GROUP MEMBERS." PROJECT TITLE: An8-bit Multiplier Circuit. COURSE NUMBER & NAME: EE-
211 Digital Logic Design. GROUP MEMBERS. Academia.edu, 13 Dec. 2012. Web. 21 Dec. 2014.
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15. HU Extension Final Project E-93 Computer Architecture
Instruction Set
The accumulator machine use 16-bit instruction format with the first five most significant bits
referred to the opcode and the rest of the bits referring to the memory location or immediate value
(operands):
opcode immediate/address
15 11 10 0
The operands can be any value up to 0x7FF. Depending on the opcode, the operands can refer to a
memory address or an immediate value. However, there are some instructions which do not require
any operands, such as RETURN, LOADAR, MOVAR, MOVAC, NOP and STORAR. For these
instructions, the operands field can be set as zero.
Below table summarizes all instructions available for the single accumulator machine with the
instruction format described above.
Name Mnemonic Operation Operands
No Operation NOP - -
Load Accumulator with Immediate value LOADA Acc SignExtImmediate Immediate
Add Immediate value to accumulator ADDA acc acc+ SignExtImmediate Immediate
Subtract Immediate value from accumulator SUBA acc  acc – SignExtImmediate Immediate
AND Accumulator with Immediate value ANDA acc  acc & SignExtImmediate Immediate
NAND Accumulator with Immediate value NANDA acc  ~(acc & SignExtImmediate) Immediate
Set if accumulator is less than immediate value SLTA acc  (acc < SignExtImmediate) ? 1:0 Immediate
Multiply Accumulator with Immediate value MULTA acc  acc * SignExtImmediate Immediate
Load Accumulator Immediate value and 0's
extend LOADAU acc ZeroExtImmediate Immediate
Load Accumulator Immediate value and shift left
by 5 bits. LOADAUP Acc ZeroExtImmediate<<5 Immediate
Add to Accumulator from Memory with value from
Memory ADD acc  acc + memory[ZeroExtAddress] Address
Subtract from Accumulator with value from
Memory SUB acc  acc - memory[ZeroExtAddress] Address
AND Accumulator with value from Memory AND acc acc & memory[ZeroExtAddress] Address
NAND Accumulator with value from Memory NAND
acc ~(acc &
memory[ZeroExtAddress]) Address
Set if accumulator is less than value from Memory SLT
acc  (acc <
memory[ZeroExtAddress]) ? 1:0 Address
Multiply Accumulator with value from memory MULT acc acc * memory[ZeroExtAddress] Address
Store accumulator content into memory STOR memory[ZeroExtAddress] acc Address
Load Accumulator with value from memory LOAD acc memory[ZeroExtAddress] Address
Shift Left Logical operation on Accumulator by 1
bit SLL acc acc << 1 -
Shift Right Logical operation on Accumulator by 1
bit SRL acc acc >> 1 -
Shift Right Arithmetic operation on Accumulator by
1 bit. This operation will preserve bit-sign SRA acc acc >> >1 -
Go to another program instruction location GOTO PC  ZeroExtAddress Address
Go to another program instruction location defined
in Address Register GOTOAR PC AR Immediate
Go to another program instruction location if ALU
produce zero result (excluding Multiplication
IFZGOTO if (zero=1) PC ZeroExtAddress Address
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16. HU Extension Final Project E-93 Computer Architecture
operation)
Procedure call CALL ARPC+2; PC  ZeroExtAddress Address
Return from procedure call RETURN PC AR -
Load Address Register with Accumulator value MOVAR AR acc -
Load Accumulator with Register Address value MOVAC accAR
Load Accumulator with value from memory
pointed by Address Register LOADAR acc memory[AR] -
Store Accumulator content to memory address
pointed by Address Register STORAR memory[AR] acc -
Increase AR register value INC AR=AR+ ZeroExtImmediate Immediate
Decrease AR register value DEC AR=AR - ZeroExtImmediate Immediate
Below are the lists of Opcode and their binary representation:
Opcode Mnemonic
00000 NOP
00001 LOADA
00010 ADDA
00011 SUBA
00100 ANDA
00101 NANDA
00110 SLTA
00111 MULTA
01000 LOADAU
01001 LOADAUP
01010 ADD
01011 SUB
01100 AND
01101 NAND
01110 SLT
01111 MULT
10000 STOR
10001 LOAD
10010 SLL
10011 SRL
10100 SRA
10101 GOTO
10110 GOTOAR
10111 IFZGOTO
11000 CALL
11001 RETURN
11010 MOVAR
11011 MOVAC
11100 LOADAR
11101 STORAR
11110 INC
11111 DEC
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17. HU Extension Final Project E-93 Computer Architecture
Assembly Language
SAM program is line-oriented. Its assembler acknowledges five types of lines: empty lines,
comment lines, instruction lines, label definition lines, and directive lines.
Empty Lines
A line that only has white spaces is an empty line. Empty lines are ignored by the assembler.
Comment Lines
All comments will start with '#' character. Block comment are not supported. Example of a
commented line:
#This is a commented line
A comment line will starts with “#” character. A label definition line consists of a label definition. A
label definition consists of “@” followed by an identifier. A directive line consists of a label
definition, followed by the name of an assembler directive, and a value to initialize the memory area
which the directive's label refers to. Lastly, an instruction line consists of an operation, followed by
operands. However, do note that not all instruction line will have an operand.
Instruction Lines
An instruction line will consist of an opcode followed by an operand, if any. Opcode needs to be in
uppercase and the following operand can be an immediate value or a label.
Assembler accepts binary, hex and character as an immediate value. However, the operand value
must not exceed 0x7FF, or 2047 in decimal since an operand can only occupy 11 bits from the 16
bits instruction.
#Example of an instruction line with an opcode and a binary value as its operand
LOADA b’11111111111
#Example of an instruction line with an opcode and a hex value as its operand
SUBA h’a
#Example of an instruction line with an opcode and a hex value as its operand
MULTA d’9
#Example of an instruction line with an opcode which does not has any operand
NOP
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18. HU Extension Final Project E-93 Computer Architecture
Label Definition Lines
A label definition line consists of “@” followed by an identifier.
#Example of a label definition. In this example, after executing the first instruction, processor will
execute the next instruction after the label “main”
GOTO main
NOP
#below line will not be executed
LOADA d’2
@main
#below line will be executed after the branch
LOADA h’1
NOP
Directives
SAM assembler used 4 directives used to allocate and initialize space for a variable: .variable,
.array, .string, .stringz. Each variable should be declared as directive line, starting with a label
definition, directive type and initial value for the variable.
Type of directive:
1. .variable
This directive will instruct the assembler to allocate one-word size variable in memory.
.variable directive uses <@label .variable immediate_value> format
#Example or declaring a variable of one-word size:
@variableName .variable h’00
2. .array
This directive will allocate a series of adjacent one-word size storage in memory. .array
directive uses <@label .array immediate_value:n> format where n is the number of memory
block the assembler needs to allocate.
#Example of reserving 10 one-word size storage in memory:
@variableName .array h’00:10
3. .string
.string directive is use to allocate adjacent memory block for storing a sequence of character.
.string directive uses <@label .string “A String”>
#Example of reserving string data type:
@variableName .string “Hello World”
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19. HU Extension Final Project E-93 Computer Architecture
4. .stringz
.stringz directive is similar to .string directive except the string will be null terminated.
#Example of reserving stringz data type:
@variableName .stringz “Hello World”
Code Snapshot
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20. HU Extension Final Project E-93 Computer Architecture
Important notes in developing assembly code for SAM
There are a few general rules which should be followed when developing code for SAM to avoid it
from behaving unexpectedly during execution:
1. Any branch instruction (GOTO, GOTOAR, IFZGOTO, CALL) should always be followed by
NOP instruction.
2. Any operation which accesses the memory (LOAD, LOADAR, STOR, STORAR, ADD, SUB,
AND, NAND, MULT) should always be followed by NOP instruction.
3. It is advisable to write all procedures at the beginning of the code since CALL instruction
can only branch up to 2048 of the memory location.
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21. HU Extension Final Project E-93 Computer Architecture
SAM Assembler
SAM Assembler is a small program used to convert the instruction written for SAM into a MIF file.
The assembler was built using C in UNIX environment. Thus, it may not compile properly if you
try it on other environment.
Building the assembler
System Requirement
Supported O/S: Ubuntu 12.04.4 LTS
Supported Gcc version: 4.6.3 (Ubuntu/Linaro 4.6.3-1ubuntu5)
Note: The code was successfully built and tested on Harvard FAS “nice” machine
1. Extract the SAMbler.c into your UNIX box
2. Run gcc SAMbler.c -o SAMbler to build the binary
Assembling the code into MIF file
Run ./ SAMbler <source file> <output file> to generate the mif file. The assembler will generate 2
files, a mif file of the source file and label.map file. The Map file contain all the labels used in the
source file and their corresponding memory location.
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22. HU Extension Final Project E-93 Computer Architecture
SAM Emulator
SAM Emulator is a Java application used to simulate the behaviour the instructions in a MIF file
when executing in SAM architecture.
System Requirement
Java Virtual Machine version: 1.7
Supported O/S: Ubuntu 12.04.4 LTS
Note: The code was successfully built and tested on Harvard FAS “nice” machine
Building the emulator
The compile script provided only works in UNIX/Linux environment
1. Extract the content of emulator directory into your UNIX/Linux machine.
2. Run ./compile.sh
Running the emulator
1. Run “java -jar SAMemulator.jar <mif File>" to run the emulator.
2. Once the emulator successfully loaded the MIF file, a help menu will be prompted
[h]elp - display this message
[s]tep - step through the program
r[e]set - restart the program
[r]un - run the program
re[g]ister - display content of all registers
run[t]ill <memory address in hex> - run the program until the PC reach a specific memory address.
Example: runtill ff
show[m]emory - display all memory content
[p]eek <memory address in hex> - show the content of a specific memory address.
[l]load <mif file> - load mif file into emulator.
e[x]it - exit this emulator
3. The emulator command can be enter in full, i.e. typing the entire word, or using a short
code, i.e. instead of typing “step”, you can enter the character “s” to execute the same
command.
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23. HU Extension Final Project E-93 Computer Architecture
Emulator Screenshot
A. Emulator command list
B. Current file being loaded into emulator
C. Current instruction being executed
D. Current registers values
E. Command prompt
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24. HU Extension Final Project E-93 Computer Architecture
DE2-115 LEDs, Buttons, Switches mapping
The table below shows the LEDs, buttons and switches mappings on DE2-115 board when running
the SAM VHDL program
Type Location Mapped to
Red LED LEDR15 to LEDR0 Accumulator content (16 bit)
Red LED LEDR17 mem_rw signal
Red LED LEDR16 mem_addressready signal
Green LED LEDG3 to LEDG0 CPU State (4 bit)
Green LED LEDG7 to LEDG5 ALU Operation signal (3 bit)
Green LED LEDG8 mem_dataready_inv
7 Segment
LED
HEX3, HEX2, HEX1, HEX0 PC value in decimal. HEX3 is hardcoded to
zero since the VHDL code can only convert 8-
bits integer to 12-bits BCD.
Slide Switch SW16 mem_suspend signal. If asserted, memory and
its clock will continue running, but it will not
respond to any memory request
Slide Switch SW17 clock_hold signal. If asserted, clock signals
generated by memory controller will be
stopped.
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25. HU Extension Final Project E-93 Computer Architecture
Appendix
SAM Architecture
SAM(v5).png
SAM ALU
ALU(v3).png
SAM Hardware Multiplier
Multiplier.png
SAM FSM
SAM_FSM2.png
*** END OF FINAL PROJECT ***
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