Different Addressing mode and RISC, CISC Microprocessor

1. Department of Computer Science & Engineering
Course Title: Computer Architecture & Organization
Course Code: CSE-322
Assignment On:
Different Addressing mode and RISC, CISC Microprocessor
Submitted to:
Rubaiya Hafiz
Lecturer Daffodil International University
Submitted by:
M M Rayhan Parvez
ID: 143-15-4617
Section: F
Submission Date: 22-03-2017

2. Different Addressing Mode
1.Register Addressing Mode:
In this type of addressing mode the instruction specifies the name of the register in which the
data is available and Opcode specifies the name (or) address of the register on which the
operation would be performed.
Example:
MOV A, B
Here the Opcode is MOV. If the above instruction is executed, the contents of Register B are moved to
the Register A, which is nothing but the accumulator.
Other examples:
ANA B
On executing the above instruction, the contents of Register B or logically ANDed with contents of
register A (accumulator).
SUB H
If we execute the above instruction the contents of Register H will be subtracted from the contents of
the accumulator.
2.Register Indirect Addressing Mode:
This is indirect way of addressing. In this mode, the instruction specifies the name of the register in
which the address of the data is available.
Example:
MOV A, M

3. SUB M
DCR M
Consider MOV A, M. This instruction will move the contents of memory location, whose address is in
H-L register pair to the accumulator.
M represents the address present in the H-L register pair. So, when MOV A, M is executed, the contents
of the address specified in H-L register pair are moved to accumulator.
3.Immediate Addressing Mode:
In this type of addressing mode the operand is specified within the instruction itself.
Let us discuss with an example.
Consider this instruction:
ADI 34H – This instruction adds the immediate data, 34H to the accumulator.
34H is the data here. H represents Hexadecimal value and the immediate value is added to the
accumulator. In this case 34H is added to the accumulator. Suppose if accumulator has a value 8H and
when this instruction is executed, 34H is added to the 8H and the result is stored in accumulator.
In the above instruction, the operand is specified within instruction itself.
4.Direct Addressing Mode:
In this mode of addressing, the address of the data (operand) is specified within the instruction.

4. There is a subtle difference between the direct addressing modes and immediate addressing modes. In
immediate addressing mode, the data itself is specified within instruction, but in direct addressing mode
the address of the data is specified in the instruction.
Example:
OUT 10H
LDA 4100H
STA 2000H
Consider the instruction STA 2000H
When this instruction is executed, the contents of the accumulator are stored in the memory location
specified. In the above example the contents of accumulator are stored in memory location 2000H.
5.Indirect Addressing:
This addressing mode utilizes the computer's ability of Segment: Offset addressing. Generally, the base
registers EBX, EBP (or BX, BP) and the index registers (DI, SI), coded within square brackets for
memory references, are used for this purpose.
Indirect addressing is generally used for variables containing several elements like, arrays. Starting
address of the array is stored in, say, the EBX register. The following code snippet shows how to access
different elements of the variable.
MY_TABLE TIMES 10 DW 0 ; Allocates 10 words (2 bytes) each initialized to 0
MOV EBX, [MY_TABLE] ; Effective Address of MY_TABLE in EBX
MOV [EBX], 110 ; MY_TABLE[0] = 110
ADD EBX, 2 ; EBX = EBX +2

5. MOV [EBX], 123 ; MY_TABLE[1] = 123
6.Implicit Addressing Mode:
There are certain instructions in 8085 which does not require the address of the operand to perform the
operation. They operate only upon the contents of accumulator.
Example:
CMA
RAL
RAR
CMA complements the contents of accumulator.
If RAL is executed the contents of accumulator is rotated left one bit through carry.
If RAR is executed the contents of accumulator is rotated right one bit through carry.
7.Relative Addressing:
For relative addressing, also called PC-relative addressing, the implicitly referenced register is the
program counter (PC). That is, the next instruction address is added to the address field to produce the
EA. typically, the address field is treated as a two-complement number for this operation. Thus, the

6. effective address is a displacement relative to the address of the instruction as shown in the example
below.
Relative addressing exploits the concept of locality.
E.g. Move X (PC), R1
Here, Contents at address X+PC are moved to R1 .X contains a constant value.
8.Index Addressing Mode:
Offset is added to the base index register to form the effective address if the memory location. This
Addressing Mode is used for reading lookup tables in Program Memory. The Address of the exact
location of the table is formed by adding the Accumulator Data to the base pointer.
Example: MOVC, @A+DPTR (This instruction will move the data from the memory to Accumulator;
the address is made by adding the contents of Accumulator and Data Pointer.
RISC and CISC architecture
What is CISC ?
A complex instruction set computer (CISC /pronounce as ˈsisk’/) is a computer where single instructions
can execute several low-level operations (such as a load from memory, an arithmetic operation, and a
memory store) or are capable of multi-step operations or addressing modes within single instructions, as
its name suggest “COMPLEX INSTRUCTION SET”.
What is RISC ?
A reduced instruction set computer (RISC /pronounce as ˈrisk’/) is a computer which only use simple
instructions that can be divide into multiple instructions which perform low-level operation within single
clock cycle, as its name suggest “REDUCED INSTRUCTION SET”

7. Understand RISC & CISC architecture with example
Let we take an example of multiplying two numbers
A = A * B; <<<======this is C statement
The CISC Approach: -
The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. This is achieved
by building processor hardware that is capable of understanding & executing a series of operations, this is where
our CISC architecture introduced.
For this particular task, a CISC processor would come prepared with a specific instruction (we’ll
call it “MULT”). When executed, this instruction
1. Loads the two values into separate registers
2. Multiplies the operands in the execution unit
3. And finally, third, stores the product in the appropriate register.
Thus, the entire task of multiplying two numbers can be completed with one instruction:
MULT A, B <<<======this is assembly statement
MULT is what is known as a “complex instruction.” It operates directly on the computer’s memory
banks and does not require the programmer to explicitly call any loading or storing functions.
Advantage: -
1. Compiler has to do very little work to translate a high-level language statement into assembly

8. 2. Length of the code is relatively short
3. Very little RAM is required to store instructions
4. The emphasis is put on building complex instructions directly into the hardware.
The RISC Approach: -
RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the “MULT”
command described above could be divided into three separate commands:
1. “LOAD” which moves data from the memory bank to a register
2. “PROD” which finds the product of two operands located within the registers
3. “STORE” which moves data from a register to the memory banks.
In order to perform the exact series of steps described in the CISC approach, a programmer would
need to code four lines of assembly:
LOAD R1, A <<<======this is assembly statement
LOAD R2,B <<<======this is assembly statement
PROD A, B <<<======this is assembly statement
STORE R3, A <<<======this is assembly statement
At first, this may seem like a much less efficient way of completing the operation. Because there
are more lines of code, more RAM is needed to store the assembly level instructions. The compiler must also
perform more work to convert a high-level language statement into code of this form.
Advantage: -
1. Each instruction requires only one clock cycle to execute, the entire program will execute in approximately
the same amount of time as the multi-cycle “MULT” command.
2. These RISC “reduced instructions” require less transistors of hardware space than the complex instructions,
leaving more room for general purpose registers. Because all of the instructions execute in a uniform amount
of time (i.e. one clock)
3. Pipelining is possible.
LOAD/STORE mechanism: - Separating the “LOAD” and “STORE” instructions actually reduces the amount of
work that the computer must perform. After a CISC-style “MULT” command is executed, the processor
automatically erases the registers. If one of the operands needs to be used for another computation, the processor
must re-load the data from the memory bank into a register. In RISC, the operand will remain in the register until
another value is loaded in its place.
Comparison of RISC & CISC

9. CISC RISC
Emphasis on hardware Emphasis on software
Includes multi-clock Single-clock
complex instructions reduced instruction only
Memory-to-memory: “LOAD” and “STORE”
incorporated in instructions
Register to register: “LOAD” and “STORE” are
independent instructions
high cycles per second, Small code sizes Low cycles per second, large code sizes
Transistors used for storing complex instructions Spends more transistors on memory registers
Example of RISC & CISC
Examples of CISC instruction set architectures are PDP-11, VAX, Motorola 68k, and
your desktop PCs on intel’s x86 architecture based too.
Examples of RISC families include DEC Alpha, AMD 29k, ARC, Atmel AVR, Blackfin,
Intel i860 and i960, MIPS, Motorola 88000, PA-RISC, Power (including PowerPC), SuperH, SPARC
and ARM too.
Which one is better?
We cannot differentiate RISC and CISC technology because both are suitable at its specific application.
What counts is how fast a chip can execute the instructions it is given and how well it runs existing
software. Today, both RISC and CISC manufacturers are doing everything to get an edge on the
competition.

10. The End