Agenda : Structure of Instruction Description of Processor Interconnection Unit Processor to memory communication RISC and CISC All about how the computer interacts with memory and processor. how they connected and work.which device how works.

1. 5- Computer Architecture

2. Structure of instruction
• Structure
– The task to be carried out by the processor
– The address or addresses in memory where the operand or operands
would be found.
– The address in memory where the result is to be stored.
– The address in memory where next instruction to be carried out is stored.
• Types of instruction
– 4-Address instruction
– 3-Address instruction
– 2- Address instruction
– 1- Address instruction
– 0- Address instruction
ADD P Q R S
What task?
(Operation
code)
Address of first
operand
Address of
second
operand
Address of
result
Address where
next instruction
would be found

3. Cont…
• 4- Address instruction
– The instruction in which four operands are there is called 4- address
instruction.
– Ex:-
– ADD a b c d
– MUL x y z q
• 3- Address instruction
– The instruction in which three operands are there is called 3- address
instruction.
– Ex:-
– ADD a b c
– SUB x y z
• 2- Address instruction
– The instruction in which two address are there is called 2- address instruction.
– Ex:-
– MOV a b

4. Cont…
• 1- Address instruction
– The instruction in which 1 operand is there is called 1 –address instruction.
– Ex:-
– MOV a
– READ a
• 0- Address instruction
– The instruction in which no operand is specified is called 0-address instruction.
– Ex-
PUSH a
PUSH a
ADD
PUSH c

5. Cont…
• If a processor has 16 different operation than 12 bits are needed to represent each
address so 12 bits are needed to represent each address.
• If length of an operand equals length of an instruction then the instruction and the
operand are said to occupy one word on computer’s memory such computer is
known as word addressable computer.
• A computer in which each byte stored can be addressed individually is known as
byte addressable computer.
Operation code Operand address
-----4-bits---- -------------------12-bits------------------

6. Description of Processor
• The processor of hypothetical computer which is known as HYPCOM. Reason
behind use of hypothetical computer is that it is easy to explain fundamental ideas
with a simple model. Real computers are too complex.
• The processor of HYPCOM has an accumulator register (ACC), instruction register
(IR), program counter register(PC).
• IR is used to temporarily store the instruction being executed. It has two parts: an
operation code part and address part.
• PC register stores the address of the next instruction to be executed.
• Other specification of HYPCOM are:
– It has 4K word addressable memory.
– A word of HYPCOM is 16 bits long.
– A word of HYPCOM stores either an instruction or data to be processed.
– It has 15 operations code.
– The instructions are single address instructions. 4 bits are needed to represent
15 operations. 12 bits are needed to store address in memory so instruction is
of 16 bits.
– It has an input unit which is used to give both instruction and data. For read
via input unit and store it in memory READ operation code is executed.
– It has a printer as its output unit which is used to output word when PRINT
operation is executed.

7. Cont…

8. Cont…
• Operation codes of HYPCOM processor.
Operation Code
(Hexadecimal)
Mnemonic
used
Meaning
1 CLA Clear ACC and place contents of specified memory
address in it.
2 ADD Add to ACC contents of specified address
3 SUB Subtract from ACC contents from specified address
4 MUL Multiply contents of ACC by contents of specified address
5 DIV Divide contents of ACC by content of specified address
and leave integer quotient in ACC
6 STO Store content of ACC in specified address in memory
7 JMP Take next instruction from given address of memory
8 JNE Take next instruction from given address if ACC<0 else
next instruction from address given in PC.
9 JZE Take next instruction from given address if ACC=0 else
next instruction from address given in PC

9. Cont…
Operation Code
(Hexadecimal)
Mnemonic
used
Meaning
A READ Input into specified address in memory data read from
input unit.
B PRINT Print data retrieved from the specified address in
memory
C SHR Shift content of ACC right by 8 bits
D COM Complement content of ACC
E EOR EX-OR operation. Match each bit of ACC with each bit
of content of specified address. If bits are identical
make the bit of ACC=0 else that bit in ACC=1
F HLT Halt computation

10. Cont…
• Opcode may be grouped by as follows:
– Data movement operation
CLA, STO
– Arithmetic operations
ADD, SUB, MUL, DIV
– Control operations
JMP, JNE, JZE, HLT
– Input/output operations
READ, PRINT
– Logical operation
SHT, COM, EOR

11. Interconnection Unit
• A set of wires which carries a group of bits in parallel is known as a bus.
• A bus which carries a word to or from memory is known as a Data bus. Its width is
equal to length of word.
• To retrieve a word from memory it is necessary to specify its address that address
is carried out by a Memory address bus whose width equals the number of bits in
MAR.
• Besides buses to carry address and data we also need control signals between the
units of a computer. Control signal issued by the processor to memory to READ or
WRITE and to I/O units to START or STOP a unit are carried by a control bus.
• A system bus is consist of a data bus, a memory address bus and control bus.

12. Cont…
• One method of connecting I/O units to the computers to connect them to the
processor via bus, it consist of a bus called DAB which specifying the addresses of
the I/O units.
• Data bus carrying a word from the addressed input unit to the processor or
carrying a word from the processor to the addressed output unit.
• Control bus carries command such as READ, WRITE, START, STOP from the
processor to I/O units. It also carries I/O unit’s status information to the processor.
• All data will be first taken to a processor register from the input unit and from
there to the memory is known as program controlled transfer.
• The interconnection of I/O units, processor and memory using two independent
system buses is known as a two bus interconnection structure.
• I/O devices are connected to a special interface logic known as Direct Memory
Access logic (DMA). It is also two bus structure. One bus connects the processor to
the memory other bus instead of connecting I/O units to the processor, connects
them directly to memory.
• Another popular method of interconnecting units is through the use of single bus
which is known as unibus system.
• In this case, the bus is shared by the three units and thus transfer of data can take
place only between two of the three unit at a time.

13. Cont…
• If the processor and an I/O unit want to use the bus at same time, only one can be
granted the bus. This decision is made by a circuit known as a bus arbitration unit.
• I/O units are given preference over the processor because I/O units have moving
parts which cannot be suddenly and if bus is not granted data may be lost.
• Main advantage of single bus system is the addressing of I/O units. These units use
the same memory address space.
• A READ instruction with an address corresponding to an input device will read data
from that device.
• It is easy to add new device as no new instructions specific to the device would be
required.
• This single bus is called the PC system bus or ISA (Industry Standard Architecture)
bus.

14. Processor to memory communication
• Following are steps for transfer data from memory to the processor
– Step 1- the processor places the address in MAR via the memory address bus.
– Step 2- the processor issues a READ command via the control bus.
– Step 3- the memory places the retrieved data in MDR and transfers it via the
data bus to the processor. Based on the read time of memory, a specific
number of processor clock intervals are allotted for completion of this
operation. During this period, the processor is forced to wait.
• For writing in memory
– The processor places the address in MAR via the memory address bus.
– The processor transmits the data to be written in memory via data bus to
MDR.
– The processor issues a WRITE command to memory via the control bus.
– The data in MDR is written in memory in the address specified in MAR.
• Main problem is mismatch between speed of processor and memory.
• This speed mismatch is alleviated by using small fast memory as an intermediate
buffer between the main memory and the processor it is known as a catch
memory.
• It is fabricated using high speed semiconductor device. Effective cycle time of catch
would be about a tenth of the main memory cycle time and its cost about 10 times
cost per byte of main memory.

15. Cont…
• Most program execute instructions in the order in which they are written is called
spatial locality of reference of instruction in a program.
• Instruction is executed there is a likelihood of the same instruction being executed
again soon is called temporal locality.
• Locality of reference is main feature which makes the use of a catch memory
effective in alleviating the speed mismatch between the main memory and
processor.
• It have two cache: Instruction cache, data cache( both are of equal size and small
compared to main memory)(size cache 64KB and main memory 64 MB)
• Block of instruction is copied in the cache memory from the main memory and
data are copied into the instruction cache and data cache respectively.
• JMP
• The block of instructions/data fetched from main memory for the storage in cache
is known as cache line. It is normally order of 16 to 64 bytes.
• There are two level hierarchy of caches.
– L1 cache
– L2 cache
• L1 cache
– First level cache is fabricated as a part of the CPU chip.
– It is known as on-chip cache or L1 cache.

16. Cont…
– The time to access a byte from L1 cache is very low. As the area of CPU is
limited the size of L1 cache is small (between 16 to 64KB).
– L1 cache itself divide into an instruction cache and data cache.
• L2 cache
– Second level cache is outside the CPU chip. It is called L2 cache.
– It uses SRAM which is faster then DRAM.
– Access time of L2 cache is larger than L1 cache. Size is of 256 KB to 512 KB and
access time is few nanosecond.
• Data first move from main memory to L2 cache and from there to L1 cache.

17. RISC and CISC
• CISC
– Goal of CPU designer to provide more and more instruction in the instruction
set of a CPU to ensure that the CPU supports more functions directly.
– It makes easier to translate high-level language program to machine language
and ensure that the machine language programs run more effectively.
– Another goal of CPU designers was to optimize the usage of expensive
memory, to achieve this the designers tries to pack more instructions in
memory by introducing the concept of variable-length instructions such as
half-word.
– CPUs with large instruction set, variable-length instructions, and a variety of
addressing modes are said to be CISC (Complex Instruction Set Computer)
architecture.
– It makes the job of machine language programmer’s easier.
• RISC
– In 1980s CPU designers realize that many instruction supported by CISC based
are rarely used.
– Complexity of CPU can be reduce by implementing only basic set of instruction
and some of the more frequently used instructions in hardware.
– Other complex instruction can be designed using this simple set of
instructions.

18. Cont…
– So decoding and execution becomes simple and fast. If the instructions are
designed in such a way that they retrieve operands stored in register in CPU
rather than from memory. This ideas have been used in designing Reduced
Instruction Set Computer (RISC).
– General steps for design RISC instructions:
1. Reduce number of instructions make them of equal length. Reduce
addressing modes. These makes decoding instructions easy. The decoding
instructions can be integrated as a part of CPU. This will enable instructions to
be decoded fast.
2. Reduce references to memory to retrieve operands. This is achieved by
increasing the general purpose registers in CPU. Operands and intermediate
results are stored in these registers. Usually 32 to 256 registers are provided
in the CPU of RISC. Only two instructions refer to the memory. First is load an
operand from memory into a register and second store result to memory. So
RISC sometimes called Load-store architecture.
3. Instructions to be executed in following steps:
I. Fetch instructions from memory.
II. Decode instructions to determine what is to be done.
III. Fetch the operand from register.
IV. Execute the instruction
V. Store the result in register.

19. Cont…
• Operands and results are stored in CPU and decoding circuit is simple then each
step takes about the same time. This allows overlapping of various stage of
instruction fetching and execution . When series of instructions are retrieved from
memory is called pipelining.
• One feature of RISC architecture is single cycle execution of most instruction.