In this file, a simple paper on computer organization will be explained, and it includes a summary of everything you need to know. u can download it from here: https://exe.io/EHdNcSP

1. Computer Organization
Computer Components & Computer functions
Introduction:
Before we talk about sub-elements, we should ask ourselves, what is Instruction fetches and
executes, Interrupts, I/O function, So the first computer is divided into three basic units
namely: input unit, CPU and output unit, then we can say that computer components are a
recent computer that established on concepts, and Computer Functions are like Data input,
Data processing, Information output, and Data storage.
1- Instruction fetches and executes:
This occurs during the first stage, decode and issue during the second, At the starting of
any instruction cycle, the processor gets the instruction from RAM, The Instruction
fetches is inserted into the IR, Any loop that fits into the cache (which was usually called
"in-stack") would run without referencing the main memory for instruction fetch,
Instruction fetches: Read instruction from the memory location into the processor, We
can define instruction execution as the process of holding an instruction by the
computer, Required action performed by the processor that reads the instruction
2- Interrupts:
- Before starting we can say that interrupts divided into classes of interrupts.
- So, classes of interrupts, virtually all computers provide a mechanism by which other
modules Input/output memory maybe interrupts the usual processing of the CPU.
So,what isinterrupt?
- The Interruptsare signalswhich have the maximumprioritized fromH/W or S/W whichthe CPU
processitssignals,Interruptsare providedprimarilytoimprove processingefficiency.
If an interrupt is awaiting, the processor does the following:
- It holds the implementation of the current program being performed and keeps its
context.
A. What are the types of interrupts?

2. - H/W Interrupts:If the signalsforthe processorisfrom an external device orH/W
- H/W interruptscanbe categorizedintotwotypestheyare:
I. Maskable Interrupt:The H/W interrupts which can be postponed when a much greatest
priority interrupt has happened to the CPU.
II. Non Maskable Interrupt:The H/W which cannot be postponed and should process by the
processor at once.
B. S/W Interrupts: S/W interrupt can split to two types, they are:
III. Usual Interrupts:the interrupts which are triggered by the S/W directives are called S/W
directives.
IV. Exception Interrupts: random interrupts while performing a program is called Exception.
3. I/O function:
- I/Omodule can define asthatitcan exchange datadirectlywiththe CPU.
- The CPU readdata or write data to an Input/outputmodule.
- Input/outputdirectivesratherthanmemoryreferencingdirectives.
I/O Interface:
An I/O interface is required whenever the I/O device is driven by a processor. Usually a CPU
communicates with devices via a bus. The interface must have the necessary logic to
interpret the device address generated by the processor.
A computer that uses memory mapped I/O accesses hardware by reading and writing to
specific memory locations, using the same assembly language instructions that computer
would normally use to access memory.] With some devices able to exchange data at very
high speeds direct access to memory (DMA) without the continuous aid of a CPU is
required.
Conclusion:
So, in the firststage the CPU getsthe instructionfromthe RAM, thenthe instructionfetchesisinserted
to the instructionregister, thenitcrossthrough( fetchcycle ), and interruptsare signalsanditgets
errorsthentellsthe processoraboutit, i/ofunctionsitexchangesdatadirectlywiththe processor.

3. Computer Organization
Interconnection structures types
Introduction:
In this topic we will talk about interconnection structures, whatis Businterconnection,
whatis Point-to-pointinterconnectionarchitecture anditsprotocol layers,whatare PCIexpress
architecture anditsprotocol layers, There are things which called interconnection
structures, so interconnection structures are connectors that connect between Major
components suchas CPU, I/O ComponentsandOutputmodule,interconnectionsuchas: Bus,
point-to-point,thenwe shouldaskourselves.
1. Bus interconnection
- It isa connectionpathconnectingtwoormore devices.
- Multiple devicesconnecttothe bus.
- Signalstransmittedbyanyone device are available foracceptance byall otherdevicesattached
to the bus.
- If more thanone device transmitsduringthe same periodtime theirsignals will become
distorted.
- a bus consistsof multiple connectionlines.
There is something is called system bus, so what is it?
- Systembusisthe busthat attachesto majorcomputercomponents
- There are linesindatabusprovide a pathwayfortransferdata amongstsystem, andthe
numberof linesdefineshowmanybitscanbe movedat a time
2. Point-to-point interconnection architecture and its protocollayers
- The sharedbus architecture wasthe standardpolicytointerconnectionbetweenthe CPUand
otherelementslike memoryandinput/output.
What is the main reason for change to point to point?
The main reasoniswas the electrical limitationsfacedwithexpandingthe frequencyof large
synchronousbuses.
The advantages of point-to-point:
i. Offers higher data rates than shared bus.

4. ii. Have multiple processors.
Protocol layers of point-to-point:
I. Physical protocol layer:Includesof wiresthatcarrythe signals,the unitof transferatthe
Physical is20 bits,whichiscalledaPhit.
II. Link layer:Responsibleforreliable transmission,The Linklayer’sunitof transferis80 bits
Flit
III. Routinglayer:Deliversthe frameworkfordirectingpacketsthroughthe fabric.
IV. Protocol:The high-level setof rulesforexchangingpackets(anintegral numberof Flits).of
data betweendevices.
3. PCI express architecture and its protocol layers:
- We can define PCIas:A common highbandwidth,givesbettersystemperformance forhigh
speedInput/outputsubsystems.
- Nowwe will definethe PCIe:Point to pointinterconnectmeanttoreplace bus-basedschemes
such as PCI.
- Keyrequirementishigh-levelcapacitytosupportthe requirementsof greaterdataaverage
Input/outputdevices.
This draw explains the PCIe:
Protocol Layers of PCIe:
I. Transaction
II. Data link
III. Physical
Conclusion:
In summary of this topic is that there are interconnection structures structures such as bus
interconnection and point to point and the bus is defined as connecting computer components
together and they are 3 basic components processor and memory and i/o component and the main
reason for changing from bus to point to point is it was the electrical limitations faced with

5. expanding and features point to Point offers higher data rates than shared bus and have multiple
processors that include 20 bits and link that include 80 bits and routing layer and the protocol and
PCIe is the type of PCI that from point to point and its protocol is transaction and data link and
physical.
Ref 1 : https://www.electronicshub.org/types-of-interrupts-and-how-to-handle-interrupts/ )
Computer Organization
Semiconductor main memory
Introduction:
In thistopicwe will talkaboutsemiconductormainmemoryandsome errorsinmemory,we
use mainmemoryto save data,but there are many typesof mainmemory, suchas RAMor
ROM or storage devices,we will know whatisRAM& ROM, and what are typesof them,and
errorsof memory.
1. Organization:
What is semiconductor? And what is consists of?
- Semiconductor memory is a digital electronic semiconductor device used for digital
data storage
- Ex: computer memory
- There is a basic element in semiconductor which name: memory cell.
What is memory cell?
- The memory cell is an electroniccircuit that stores one bit of binary information and it must
be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level).
Its value is maintained/stored until it is changed by the set/reset process. The value in the
memory cell can be accessed by reading it.
- The cell has three functional terminalsabletocarry an electrical signal.
- The choice terminal selectsamemorycell forreadingorwritingoperation.
- The control terminal refersreadorwrite,forwritingthe otherterminal givesanelectricalsignal
2. DRAM and SRAM:
RAMDividedintoDRAMand SRAM, soDRAM referstoDynamicRAMand SRAMrefersto Static
RAM.
A. DRAM:
- Made fromcellsthatcaches data as charge oncapacitors.
- DRAMshouldbe refreshedcharge periodicallytomaintaindatastorage.

6. - In DRAMhigh voltage represents1,and a low voltage represents0
B. SRAM:
- Digital device usesthe same logicelementsthatusedinthe CPU.
- It holdsdata whenpowerissuppliedtoit.
4. DRAM and SRAM:
- Are volatile.
- Powermustsupplytothe memorycontinually.
5. D-Cell:
- Easy to build.
- Smaller.
- Lessexpensive.
- Usedfor mainmemory.
6. S-Cell:
- Faster.
- Usedfor cache memory.
3. ROM & Types of ROM:
- ROM means(Readonlymemory),ROMisdifferentfromRAM,ROMcan save data when
computeristurnedoff.
- Data is alwaysinmainmemory andneverneedstobe loadedfroma secondarystorage device.
A. Disadvantages:
- If any bitis wrongthe whole batchof ROMmust be thrown.
- Data insertionincludesarelativelylarge fixedcost.
B. PROM:
- It isa type of ROM, not expensive,Nonvolatile, Provides flexibility.
C. EPROM:
- Erasable programmable read-onlymemory, more expensivethanPROMbut hisadvantage is
the multiple update capability
D. EEPROM:
- Electricallyerasableprogrammable read-onlymemory, More expensivethanEPROM
E. Flash-Memory:
- mediumbetween EPROMandEEPROMin theircostand functionality
- Microchipis organizedsothata sectionof memorycellsiswipedoutinasingle action

7. 4. Interleaved memory:
- consistsof a collectionof DRAMchips.
- Groupedtogethertoforma memorybank.
- Everybank is separatelyable toservice amemoryreador write order.
5. Error correction techniques:
- the semiconductormemorysystemissubjecttoerrors.
- These can be classifiedashardfailuresandsoftbugs.
6. Memory failure types:
- memory failure: refer to the wrong recall, or complete loss, of information in
the memory system for a specific detail and/or event.
- Memory errors may include remembering events that never occurred or remembering them
differently from the way they happened, and types are:
A. Hard Failure:
- physical defectalways.
- Memorycell affectedcannotreliablystore data.
B. Soft Error:
- non-destructive event thatchange the contentsof one or more memorycells.
- short corruptiontomemory.
Conclusion:
In the end we learned that semiconductors is electronic semiconductor device and uses for data
storage such as computer memory and there is a basic element in it which is memory cell and
memory cell is an electronic circuit stores one bit of binary information and there are types of
ram such as DRAM and SRAM and DRAM is dynamic RAM and it has been made from data-
bearing cells as a charge in capacitors and there is also in DRAM high voltage represents 1 and a
low represents 0 and SRAM is static RAM and it digital device this use the same logic elements
that used in the CPU and its advantages is that it can retain data when power is out, as well as
the advantages of DRAM and SRAM that are volatile and power must supply to the memory
continually features dynamic cell that easy to build and smaller etc. Static cell is faster and used
for cache memory and there are types of ROMsuch as PROMEPROM EEPROMand Flash
memory and there is an interleaved memory that includes DRAM chips and grouped together
to form a memory bank and we can get errors in memory such as hard and failure error.

8. List of references:
Ref 2 : https://en.wikipedia.org/wiki/Memory_cell_(computing)
Ref 3 : https://en.wikipedia.org/wiki/The_Seven_Sins_of_Memory
4203 Computer Organization
Microprocessor 8086
Introduction:
- In thissubjectwe will talkabout,8086 Microprocessorisan enhancedversionof
8085Microprocessor that was designedbyIntel in1976, we will know whatMicroprocessor
8086 is,The parameters,lengthandoperandaddressing,typesof itsarchitecture,How many
bitsitsCPU, How manybitsaddress?, Typesof flags,Typesof general registers,Memorysize,
The variousinterrupts.
i. What is microprocessor 8086?
- 8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed
by Intel in 1976.
ii. The parameters, length and operand addressing:
Addressingmodes are anaspectof the instructionsetarchitecture inmostCPU designs, The various
addressingmodesthatare definedinagiveninstructionsetarchitecture definehow the machine
language instructions inthatarchitecture identifythe operand(s) of eachinstruction.Anaddressing
mode specifieshowto calculate the effective memoryaddress of anoperandbyusinginformation
heldin registersand/orconstantscontainedwithinamachine instructionorelsewhere.
3. types of its architecture:
a) The bus interface unit
b) Instruction Pointer
4. How many bits its CPU?
- A 16-bitCPU
5. How many bits address?
- 20 bits
6. Types of flags:
SignFlag, ZeroFlag,AuxiliaryCaryFlag,ParityFlag, CarryFlag,Overflow Flag
7. Types of general registers:

9. AX,BX, CX,DX
8. Memory size:
- 1MB
9. The various interrupts:
a) Hardware Interrupts:There are twohardware interruptsin8086 microprocessors.Theyare:Non
Maskable Interrupt:Itisthe highestpriorityinterruptin8086 microprocessors, InterruptRequest: It
providesasingle interruptrequestandisactivatedbyI/Oport.
b) Software Interrupts:There are 256 software interruptsin8086 microprocessors.