1. Matisse Chen
_________________________________________________________
Address: 24 Dusty Rose, Irvine, CA 92620
Home phone: 949-387-7846 ; email: matissechen@gmail.com
Strength And Accomplishments:
15+ years field technology service with TSMC’s No.1 and top 5 customers that achieved
numerous new technologies ramping including TSMC’s first tape-outs in 65nm, 45nm,
28nm, and 40eFlash, etc. Superior professional supports to all design communities
including technology, CAD, memory, libraries, I/O, and chip teams. Specialty
technologies (RF, HV, and low power) and package specialty to find the best cost-
performance balance solution through from SiP/PoP to Fan-in/Fan-out.
Profession Highlighs:
 Complete circuit design training and chip implementation experience
- Chip-lead designer for TSMC’s 0.13 DFM (Design For Manufacturing) project.
Complete design experience from circuit design, simulation, layout, DRC, LVS,
verification, testing and analysis.
 The most outstanding mixed-signal and memory process debug expert
- Award the first TSMC’s most outstanding product engineer (2002),
- Extremely good at data analysis especially on complex cases that might combine
multiple factors from design, layout, and process.
 Backend technology and business expert
- Account manager for QCOM’s turnkey business with TSMC
- Account manager for IR’s turnkey business with TSMC
- Build up the assembly line and system in China in 1996.
 Big data mining expert
- Unix shell scripts, Perl, Python, EXCEL VBA, SPICE simulation, etc to facilitate
technology benchmark and cost cross-over analysis.
Working Experience:
 2012 April to now: BRCM’s Sr. Principle Engineer, Process Development
- New technologies foundry support champion
(16FF/20SoC/28HPC+, 40eFlash, 0.13BCD HV, etc)
- Best PPA/Cost technology solution provider
(technologies cross-over analysis, SOC/SiP/PoP cost analysis)

2. - PDK Design support
(Synopsys flow, Cadence flow, Timing sign-off, Signal Integrity, etc)
- New technology pilot product NPI (new production introduction)
(AVS, power reduction, Vccmin optimization, systematically defect reduction, etc)
- Design process chaos yield issue FA expert
- Unix Shell script, awk, Perl, Python, MS EXCEL VBA expert
- Data mining expert: yield improvement, SRAM Vccmin, power reduction, process
optimization
 2011 to 2012: Technical Manager for TSMC Southern CA mid-size and
emerging accounts technical account support
- Semiconductor technology service including technology choice, design rule
discussion, Lib/IP and design tech files support, etc.
- Customer market analysis, product roadmap, manufacturing, and pricing
 2003 to 2011: Technical Manager for TSMC top customer
- Focus on local support and leading edge JDP project from N65 to N28
- Advocate customer voice to TSMC integration and RD teams like process
variation methodology enhancement, quality control for SPICE or DRM change
notes, etc.
- First tape-out success and first mass production for N65 and N45
- On-site support for fully communication with designer, device, SPICE, product
engineering, and CAD teams
- Special capability on technology migration and cost analysis
- Full turnkey service account support including CP/FT, OSAT sourcing,
qualification and pricing.
- Pricing coordination
 2002 to 2003: TSMC Mixed-signal Specialty Product Engineer
- Mixed-signal electrical failure analysis specialist with the knowledge and skills on
ATE tester data collection and analysis, process variation, layout or design circuit
analysis to identify the root cause to improve the yield or process
- Fab matching specialist (mixed-signal related process)
- DFM (Design For Manufacturing) PE project owner that own a budget to tape-out
the first TSMC DFM chip to study known DFM effects at that time including LOD,
PSE, etc.
- Award the first TSMC’s most outstanding product engineer (2002),
 1998 to 2002: TSMC Fab3 Product Engineer
- Yield improvement by close cooperation with fab integration, fab module, and
testing teams.
- Keep on the top 20% performance staffs in every year.
- Being group leader from the 2nd year (0.30/0.35um VLSI Logic team).

3. - Dana analysis and tool development expert (UNIX programming, Perl, EXCEL
macros, etc.)
 1994 to 1996: China Project Engineer on Siliconix Semiconductor (acquired by
Vishay)
- Bring-up a new assembly and testing house on China Shanghai for power IC and
discrete. Set up the planning, MIS, and QC system that eventually qualify the
QS9000 certification.
SpecialTrainingReceived:
- Analog IC design
- RF circuit design
- Nyquist rate data converter
- Base-band chip design
- Fundamental communication system
- Unix shell programming
- Solaris administration
- Agilent and Teradyne mixed signal and RF test.
- Agilent HP 93K ATE Digital test.
- Catalyst Mixed signal IC test.
Education:
M.S.E.E. (1996 –1998) National Tsing-Hua University, Taiwan
B.S. Physics (1989-1992) National Tsing-Hua University, Taiwan