1. Ken Naumann 925-487-3249
2317 Alsace Court, Livermore, CA 94550
Professional Profile
Cisco Catalyst 2k,3k,4k Switch
Hardware Designer
Cross-Functional Technical Team
Leader
Co-innovator in new Ethernet signaling
and power technology
Ethernet PHY and channel expertise
Co-definer of Cisco ASIC/PHY
interface USXGMII/QSGMII
Extensive Coding Theory: 8b/10b,
64b/66b,Viterbi, LDPC, THP, Trellis
Problem Solving and Simulation
capability using MATLAB
Test Automation System Designer
ProfessionalExperience
Cisco Systems, San Jose, CA
April 2005-Current
Catalyst Switching Technical Leader
Achievements:
Enterprise Switch co-innovator and inventor in mGig new generation of
Catalyst switches
Designed CAT3k,4k Enterprise Fixed Switches: 48 port mGig switch; 12-
port 10Gbs Fiber Aggregator; 48-port 1Gbs Switch; 8 x 10Gbs Fiber
Uplink module; 2 x 10Gbs Copper Uplink module
Designed Ethernet 10Gbs UPoE/Data test system for concurrent testing of
10Gbs Line Rate + UPoE over full channel
Lead a key Next-generation Switch ASIC Qualification for Enterprise
switching portfolio
ASIC/PHY USXGMII Interface Co-author + Patent
Wrote 1Gbs and 10Gbs Cable Diagnostics specification and worked with
PHY vendors on verifications and enhancements
IEEE NBase-T participant and influencer
Co-defined 10G/UPoE Line Transformer + Patent
Lead MGig Channel Evaluations cat5e,cat6,cat6a
Designed and implemented Ethernet PHY tri-speed Automated Test Suite
Lead Multiple 1Gbs and 10Gbs PHY Qualifications for Switching/Routing
across multiple Cisco Business Units
Responsibilities
Technical Leader of Cross-functional Development teams
Ethernet Switch Hardware Design and Development Lead
Influencer of Architectural decisions working with Architecture Lead
Defined and conducted Channel evaluations using new mGig Technology
Conducted Ethernet PHY evaluations
2. Ken Naumann925-487-3249[e-mail]
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Conducted Switch ASIC evaluations
Keyeye Communications, Sacramento, CA
August 2004 – April 2005
Staff Applications Engineer
Achievements:
Designed and validated 10GBase-T PHY Demo Board that interfaced to
Ixia Traffic Generator/Analyzer System
Authored 10GBase-T PHY Data Sheet and Application Note
Conducted 10GBase-T PHY setup and demonstration for Venture Capital
Executives, Company Board personnel, and Trade Shows
Conducted comprehensive Ethernet Channel Analysis and testing
Defined 10Gbs PHY Qualification Plan for key customers like Cisco
Systems
Responsibilities
As Technical Leader handled all Internal and External Applications issues
Worked with Silicon Design team on feature validation and bug resolution
Presented Technical Pre-Sales collateral to target customers
Worked with Marketing on creating technical white papers
Drove all technical issues associated with “Design-in” activities at
customer site
San Jose State University
January 2003 – June /2004
MSEE Digital Communications
Completed remaining MSEE courses and Masters Project
Received MSEE Degree June 2004
Broadcom Corp. San Jose, CA
December 2000 – November 2002
Field Applications Engineer
Achievements:
Drove Technical Design of key PHY and Switch silicon into Nortel
Networks and Extreme Networks Enterprise and Data Center systems
Drove Design of PHY and Switch silicon into SMB provider Netgear
Worked with design team to demonstrate new Cable Diagnostic tools for
Gigabit Ethernet PHYs
Worked with design team on Transmit Distortion evaluations using Data
Acquisition instruments and Matlab post processing
Responsibilities:
Assisted customer with technical guidance on silicon design into target
3. Ken Naumann925-487-3249[e-mail]
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system and problem solving
Worked with Sales Management and customers on achieving best system
solution based on technical goals and cost metrics
Conducted system design and layout reviews and recommended design
improvements
Provided on-site debug for customer issues
Created debug scripts
Ran Demo’s in house and at customer site
National Semiconductor, Santa Clara, CA
January 1993 – December 2000
Staff Field Applications Engineer
Achievements:
Designed-in NS486 microprocessor at Cisco
Designed in LAN PHY silicon at Cisco
Designed-in LAN PHY/Twister silicon at Sun Microsystems
Designed-in GE PHY/Controller at Netgear
Designed in Analog power and Interface silicon at several smaller
customers
Worked on thin client designs using Cyrix microprocessor
Conducted key custom traffic studies for NIC and Switch designs for
several customers including Cisco, Sun, Netgear to help solve problems or
prove performance
Wrote white papers on DSL and Ethernet technology
Wrote simple C language programs for micro-controllers
Responsibilities:
Lead FAE for a top strategic account Cisco Systems
Assisted customers in Ethernet system design
Assisted customers in PC architecture and system design
Assisted customers in Analog Power design
Trained FAE’s in Networking
Ran Demo’s in house, at customer site, and at Trade Shows
Education
San Jose State University, San Jose, CA
MSEE, Digital Communications, 2004
San Jose State University, San Jose, CA
BSEE, 1992
References
References are available upon request.