1. Shwo-Tsai Jason Chen
(H) 408-517-8899 (C) 408-796-8973 1122 Milky Way
Email: jasonchen888@gmail.com Cupertino, CA. 95014
I can provide the best value to your open position, through my 19+ years of
technical experience in analog, digital and mixed-signal CAD development, as well
as management skills in planning, leadership, mentoring & communication.
Executive Summary:
Functional management experience: I led a team of 6 developers which as a team
successfully built up infrastructures, procedures and workflows used by the group. This
allows the group to deliver layout verification runsets and Parameterized Cells (PCells)
for more than 10 process technologies, each within a 3-week cycle time. Results quality
were tracked as an annual increment of error coverage of 50%, while reducing reported
customer issues by 50%.
Program management experience: Managing Process Design Kit (PDK) development
teams of 6 developers, achieved on-time delivery of more than 20 different PDKs,
comprised of bipolar, CMOS and BiCMOS process technologies from 130nm to
650nm. Each PDK consists of symbols, Component Definition Format (CDF),
callbacks, PCells, layout verification runsets and Intellectual Property (IP) libraries.
Hands-on experience in C-shell scripts, Cadence SKILL programming, PCells
programming, layout editing, layout automation tools & flows, physical verification
runsets and tools in Assura & Hercules.
Key characteristics of good customer orientation, discipline, self-motivation, high
flexibility, and teamwork. The results were demonstrated in consistent execution and
successful collaborative projects among various groups including Process Technology,
Modeling and product lines, to standardize PDK development methodologies.
Took managed risks to automate PDK development and built reliable, flexible
procedures & checklists to improve quality and cycle time. I routinely utilized problem
solving skills and root cause analysis to prevent issue reoccurrence.
Provided mentorship and tailored development plans for each direct report, to
measurably improve not only technical skills, but also broadened their scope of project
leadership, communication and interpersonal skills.

2. Core Competencies:
• Process Design Kit (PDK) development and management.
• Cadence Parameterized Cells, (PCell), Virtuoso Layout Editor, Virtuoso Customer
Router, Assura verification tools, Design Rule Check (DRC), Layout Versus
Schematic (LVS), Electrical Rule Check (ERC), Antenna Rules Check (ANT),
Resistance Capacitance Extraction (RCX).
• Synopsys Hercules verification tools, Star-RCXT, Astro Place & Route (P&R),
Milkyway Database.
• Microsoft Office (PowerPoint, Excel, Word), Microsoft Project.
• Problem solving, root cause analysis, functional and project management skills.
Professional Experience: Sept 1989 - Mar 2009, as list below, all in National
Semiconductor Corp, Santa Clara, California
Senior CAD Engineering Manager: August 2004 – March 2009
• Managed a team of six (6) engineers for developing physical verification (DRC, LVS,
ERC, ANT) & parasitic extraction (RCX) runsets in Assura & Hercules. These runsets
were delivered on schedule, as part of PDKs, to support more than 20 processes
technologies, including bipolar, CMOS and BiCMOS. Built up consistent runset
development methodologies and continuously monitored across all process technologies.
• Persistently drove major projects with results in: RCX Accuracy Improvement,
Verification Runsets Standardization, and PDK Development & QA Automation.
• Collaborated with Process Technology & Modeling groups, and key product line users to
drive common standards in verification runsets, layers and manufacturing specifications.
• Led a cross-functional team project whose goal was to bridge the expertise in verification
runsets with statistical analysis and reliability data to improve product yields and stability.
CAD Engineering Manager: December 1998 – July 2004
• Managed a team of five (5) engineers for developing Parameterized Cells (PCells) and
layout automation related runsets to support Cadence Virtuoso Layout and Custom Router
tools. Hosted Layout Users Forum to improve PCells, tools & flow usage models.
• Standardized and modularized PCell programming to improve development cycle, quality
and avoid issue reoccurrence, across 20 process technologies.
• Evaluated layout automation and layout productivity improvement tools. Defined and
deployed analog and mixed-signal tools, flows & methodologies for all product line users.
• Managed PDK development teams, with customer engagements, to deliver 20 PDKs
annually, which include symbols, CDF/callbacks, PCells, verification runsets and IP
(Intellectual Property) libraries which consist of standard, I/O and Memory cells.

3. Staff CAD Engineer: August 1997 – November 1998
• Led analog & mixed-signal Place & Route projects to define tools, flows and
methodologies with improved layout cycle time. Created analog and BiMCOS device
PCells (MOS, BJT, resistor, capacitor) & macro PCells (Diff Pair, Cascode).
Senior CAD Support Engineer: January 1996 – July 1997
• Provided full CAD support to Telecom Division from design entries to tape-outs.
Converted ISpice netlists to Opus schematics. Wrote C-shell scripts to reformat to CDL
netlists to be Diva LVSable. Ran Dracula Layout Parasitic Extraction, and performed
mixed-mode simulations. Generated timing-driven flow for 0.6um tape-out products.
Intermediate/Senior Product Engineer: September 1989 – December 1995
• Worked in ASIC Division to perform yield analysis based on characterization & statistical
results, reliability tests including burn-in/ESD/latchup, failure analysis to debug device
problems. Worked on turn-key designs to import schematics with ASIC macro libraries,
ran Verilog pre/post-route simulations, Cadence Place & Route and generated test vectors.
Education:
M.B.A. in Project Management, Golden Gate University, S.F, December 1998.
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M.S. in Electrical Engineering, University of Southern California, L.A., May, 1989.
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B.S. in Electronic Engineering, Chung-Yuan University, Taiwan, R.O.C, June, 1985
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References & Recommendation Letter: Available upon request.
Others: US Citizen