This document provides a summary of Ray Simar Jr.'s qualifications and experience. It outlines his over 25 years of experience in the semiconductor industry and decade of experience in academia, entrepreneurship, and consulting. It highlights his pioneering work developing DSP architectures at Texas Instruments, including being the principal architect of three major DSP product lines. It also summarizes his current role as a Professor in the Practice at Rice University where he teaches and mentors students in computer engineering, digital signal processing, and neural networks fields.

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RAY SIMAR JR.
CONTACT INFORMATION: ray.simar@rice.edu mobile: (713) 446-7338 office: (713) 348-2257
QUALIFICATIONS
More than 25-years of experience in the semiconductor industry and a decade in academia, entrepreneurship, and
consulting, hallmarked by:
• Pioneering innovations in DSP architecture - principal architect of three major DSP product lines enabling multi-
billion dollars per year of revenue and tens of millions of units shipped per year
• Leadership of innovative engineering teams - design manager of three major product lines, managing cross
functional teams that created numerous innovations in design methodology and programming tools
• Professor in the Practice - educating and mentoring thousands of Rice students in the fields of computer
engineering, digital signal processing and neural networks
• Entrepreneurship in academic startup incubators, iPhone applications, and prototype development
• IEEE Fellow and ACM Distinguished Engineer with more than twenty-five patents in computer architecture and
neural networks
PROFESSIONAL EXPERIENCE
PROFESSOR IN THE PRACTICE ― Rice University, Houston, TX
Department of Electrical and Computer Engineering 2009-current
CONSULTANT AND EXPERT WITNESS 2009-current
• Cirrus Logic consultant 2018-current
• Octavo Systems consultant 2017
Exploratory work on mixed-signal computer architectures, patents pending
• Texas Instruments: Expert witness on several cases. 2009-2018
PRESIDENT AND CO-FOUNDER OF REBEL PUTTER, LLC ― Richmond, TX 2014-current
ACADEMIA AT RICE UNIVERSITY
FACULTY SENATE – current member, elected in 2018
Hold representative seat for non-tenure track faculty
AWARDS AND GRANTS
• School of Engineering’s Curriculum Innovation Award for pedagogical innovation 2018
• Development and Enhancement Teaching Grant for scaffolding 2017 and 2019
• Brown Teaching Grant fostering excellence in undergraduate teaching 2015 and 2017
RESEARCH
• VIP - Vertically Integrated Projects: teams of undergrad and graduate students working on multi-year projects
• PACE – DARPA funded program for Configurable Compiler infrastructure
COURSES TAUGHT
• COMP/ELEC 425/554 – Computer Systems Architecture: Topics include advanced pipelining, memory hierarchy,
ARM and RISC-V
• ELEC 220 – Fundamentals of Computer Engineering: Introductory overview including topics of data types, op-
codes, pipelining, RISC-V, and hands-on microprocessor use
• ELEC 542 – DSP and Vector Spaces: Advanced topics including orthonormal bases, Hilbert spaces, regulariza-
tion, adaptive filters, and neural networks
• ELEC 431 – Digital Signal Processing: Fundamental and advanced topics including derivation of LTI systems,
Nyquist-Shannon sampling theorem, fast discrete Fourier transform, filter design
DIVISIONAL ADVISOR
School of Engineering mentor for all engineering students in Martel and 2013-current
Jones residential colleges
CO-DIRECTOR RICE CENTER FOR ENGINEERING LEADERSHIP 2012-2016
OWLSPARK BOARD OF DIRECTORS 2013-2016

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ENTREPRENEURSHIP
OWLSPARK ACCELERATOR – Lean Launch Pad based ― Rice University, Houston, TX Summer 2014
• Faculty member of the two-person team Jedi Putter/Rebel Putter
• Team developed new technology supporting prototype development
REBEL PUTTER, LLC Fall 2014
• Sponsored a senior design team in the Rice Oshman Engineering Design Kitchen
• Developed network of key providers of technology and manufacturing
• Application release to the Apple app store (www.rebelputter.com). Current focus is on the first hardware MVP
(Minimum Viable Product), the X-1
KEY TECHNICAL INNOVATIONS
TEXAS INSTRUMENTS’ VLIW DSP FAMILY ― PRINCIPAL ARCHITECT 1992-2009
The TMS320C6x is TI’s family of scalable VLIWs. The scalability made possible six distinct generations of the family:
• C62x ― The C62x family of VLIWs was the first member of the family. Key features of note included:
• 8-wide VLIW with dual RISC-style datapaths performing 16, 32, and 40-bit operations
• Conditional/speculative execution of all instructions
• Exposed deterministic pipelines supporting clock rates from as low as 150 MHz to as high as 1.2 GHz
• C67x ― Added to the C62x architecture support for single-precision and double-precision floating-point calcu-
lations
• C67x+ ― Added additional floating-point units and increased the register file size of the C67x
• C64x ― Added to the C62x architecture support for video data calculations
• C64x+ ― Added code size reduction instructions to the C64x
• C647x ― A merging of the C62x, C67x+, and C64x+ architectures
INDUSTRY’S FIRST PARALLEL DIGITAL SIGNAL PROCESSOR ― PRINCIPAL ARCHITECT 1989-1992
The TMS320C4x family of DSPs was the industry’s first family of DSPs with support for building parallel-processing sys-
tems. User could build systems ranging from simple pipelined configurations to multidimensional networks. Key inno-
vations include:
• First DSP with dedicated communication-ports for direct processor-to-processor communication
• Novel DMA architecture supported processor-to-processor communication concurrent with DSP CPU computa-
tions
INDUSTRY’S FIRST DSP WITH AN INTEGRATED DMA ENGINE
AND FIRST CMOS FLOATING-POINT DSP ― PRINCIPAL ARCHITECT 1985-1988
The TMS320C3x family of DSPs was the industry’s first family of floating-point DSPs to be implemented in CMOS tech-
nology, providing a high performance and a low power breakthrough. Key innovations, that are now common in the
industry, included:
• First DSP with an integrated DMA engine enabling, for the first time, concurrent DSP computations and data
transfers
• First DSP with a program cache
• First DSP with two data address generation units
TECHNICAL LADDER
ACM DISTINGUISHED ENGINEER - 2013
“In recognition of significant accomplishments in, and impact on, the computing field.”
IEEE FELLOW - 2011
Recognized “for leadership in digital signal processor architecture development.”
IEEE SENIOR MEMBER - 2009
THE TEXAS INSTRUMENTS TECHNICAL LADDER - Positions and Year of Election
• Fellow - 1997
• Distinguished Member of Technical Staff - 1997
• Senior Member of Technical Staff - 1989
• Member of Group Technical Staff - 1987

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DESIGN MANAGEMENT AND LEADERSHIP
LEADER OF RAPID ARCHITECTURE DEVELOPMENT TEAM 2004-2009
Led a cross-functional, cross-organizational team of experts in the areas of compilers, simulators, and design, working
on a methodology for dramatically improving how processors are developed. Accomplishments of the team included:
• Showed feasibility of dramatically shrinking product development time from more than two years to less than
nine months
• To enable this vision, put together a rapidly reconfigurable tool chain and a parameterized processor genera-
tion flow
MANAGER OF ADVANCED ARCHITECTURE TEAM 1997-2006
Managed cross-functional team consisting of design, process, simulator, and architecture experts. Accomplishments
included:
• Extended the C67x to create the C67x+
• For the consumer-audio market, defined a C67x+ based chip. With the involvement of the compiler team, the
new architecture and implementation approach resulted in a 40% area reduction and twice the application per-
formance.
• Developed a new instruction encoding scheme for the C64x+. Code size reduced 30% for cost-sensitive appli-
cations.
• For the DSL market, developed a new family of low-power, low-cost implementations of the C62x family
• Developed new architectural evaluation tools whose capabilities included a simulator with the new ability to
display memory access patterns over time and a new trace capability supporting backward steps in time
CORPORATE STEERING TEAMS 1997-2006
• Led Corporate Interconnect Initiative CLASSIC – Coding, Logic, Architecture, and Systems Solutions to Inter-
connect Challenges
o Organized and chair two corporate wide symposiums to address chip interconnect challenges and
the end of Moore’s Law
• A member of other steering teams: Competitive Intelligence Team, DSP Roadmap Team, Energy Efficient
Steering Team.
DESIGN MANAGER OF TMS320C6X 1992-1996
Coordinating the design, application, software tools, and marketing teams. Key accomplishments of the program in-
cluded:
• TI’s first synthesis flow for building programmable DSPs
• TI’s first FPGA-based emulation flow for design verification
• The first high performance VLIW DSP compiler. This compiler dealt with new key problems such as register-file
partitioning and support for software pipelining to reach peak performance with small code size
• First new DSP product to have silicon, software tools, and documentation available at product announcement
DESIGN MANAGER OF TMS320C4X 1988-1992
Coordinating the design, application, software tools, and marketing teams. Key accomplishments of the program in-
cluded:
• TI’s first parallel debugger supporting distributed breakpoint capability across multiple processors
• TI’s first parallel linker supporting linking of program and data for multiprocessor systems
• Developed a four processor evaluation-board to support customer prototyping of multiprocessor systems
DESIGN MANAGER OF TMS320C3X 1985-1988
Coordinating the design, application, software tools, and marketing teams. Key accomplishments of the program in-
cluded:
• Transitioned DSP process technology from high-power NMOS to low-power CMOS with a performance gain
• TI’s first DSP to have a functional model written in a register-level modeling language supporting easier design
verification

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CORPORATE AND GOVERNMENT AFFAIRS ― Texas Instruments, Houston, TX
LICENSING AND VENTURE CAPITAL TECHNICAL ADVISOR 1997-2009
Worked with licensing and venture capital team to provide technical assessment of third parties’ technology
TECHNICAL LEAD ON TI’S DSP EXPORT-CONTROLS TASK FORCE 2000-2002
Technical lead in DSP export control discussions and negotiations with the U.S. Department of Defense, National
Security Council, and the Information Systems Technical Advisory Committee (ISTAC). Successfully built the case
that convinced the US administration to remove all export controls on all microprocessors, including DSPs.
EXPERT WITNESS IN PATENT LITIGATION 2001-20012
On four occasions, deposition taken in cases of patent litigation. On one of these occasions, also had the role as
primary spokesperson for Texas Instruments.
MEDIA RELATIONS AND MARKET COMMUNICATIONS
TECHNICAL SPOKESPERSON 1988-2009
Regularly asked to be a technical spokesperson spanning the range from product introductions to discussing
technology trends:
• Interviewed by the press including: Rice University’s Sallyport, EE Times, Electronic Design News, Dallas
Morning News, CNET News, Microprocessor Reports, Electronic Design, Electronic News, RTC Magazine,
ECN Magazine, and others
• Meeting with industry analysts including: BDTi, Forward Concepts, Dataquest, and others
• Presenter at TI Developer’s Conferences
CUSTOMER INTERACTION 1988-2009
100s of customer visits. Visits often dealt with the introduction of new products and listening to customers
needs.
OTHER ASSIGNMENTS
MENTORING 1997-2009
Participated in formal targeted mentoring programs for members of the technical ladders, future leaders, and
new employees. Served as an informal mentor to many junior engineers.
DSP-APPLICATION ENGINEER 1983-1985
Early member of the original TMS320 application engineer team, one of the first DSP application teams in the
industry. Accomplishments included:
• Wrote TI’s first two DSP application notes
• Member of the original team developing the TMS320C3x family
PUBLICATIONS, PRESENTATIONS, AND PATENTS - details available upon request
• Publications and Presentations: 57
• US Patents: 27 granted as inventor and coinventor
• Patents pending in the areas of mixed-signal computers and golf
EDUCATION AND AFFILIATIONS
• Master of Science, Electrical Engineering ― Rice University, Houston, TX, 1983
Thesis Title: “Surface Reconstruction from Surface Contours”
• Bachelor of Science, Bioengineering - Summa Cum Laude ― Texas A&M University, College Station,
TX,1981
University Undergraduate Fellow Thesis: “A Computer Model of the Coronary Circulation”, recipient
of the Senior Honors Thesis Prize
• Member: IEEE, ACM, Tau Beta Pi

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PATENT LIST (27 GRANTED)
U.S. PATENT
NUMBER
PATENT TITLE
7,039,790 Very long instruction word microprocessor with execution packet spanning two or more fetch pack-
ets with pre-dispatch instruction selection from two latches according to instruction bit
6,895,494 Sub-pipelined and pipelined execution in a VLIW
6,625,719 Processing devices with improved addressing capabilities systems and methods
6,411,984 Processor integrated circuit
6,374,346 Processor with conditional execution of every instruction
6,321,318 User-configurable on-chip program memory system
6,182,203 Microprocessor
6,055,628 Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks
5,983,328 Data processing device with time-multiplexed memory bus
5,964,825 Manipulation of boolean values and conditional operation in a microprocessor
5,958,044 Multicycle NOP
5,907,864 Data processing device with time-multiplexed memory bus
5,841,379 Method and apparatus for selectively counting consecutive bits
5,826,101 Data processing device having split-mode DMA channel
5,809,309 Processing devices with look-ahead instruction systems and methods
5,751,991 Processing devices with improved addressing capabilities, systems and methods
5,594,914 Method and apparatus for accessing multiple memory devices
5,535,348 Block instruction
5,511,146 Excitatory and inhibitory cellular automata for computational networks
5,410,652 Data communication control by arbitrating for a data transfer control token with facilities for halting a
data transfer by maintaining possession of the token
5,390,304 Method and apparatus for processing block instructions in a data processor
5,305,446 Processing devices with improved addressing capabilities, systems and methods
5,179,689 Data processing device with instruction cache
5,175,841 Data processing device with multiple on-chip memory buses

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U.S. PATENT
NUMBER
PATENT TITLE
5,109,351 Learning device and method
5,099,417 Data processing device with improved direct memory access
4,912,636 Data processing device with multiple on chip memory buses