High Speed, Broadband Amplifiers

1. 6.976
High Speed Communication Circuits and Systems
Lecture 5
High Speed, Broadband Amplifiers
Michael Perrott
Massachusetts Institute of Technology
Copyright © 2003 by Michael H. Perrott

2. M.H. Perrott MIT OCW
Broadband Communication System
ƒ Example: high speed data link on a PC board
- We’ve now studied how to analyze the transmission line
effects and package parasitics
- What’s next?
VL
C1 RL
L1
Delay = x
Characteristic Impedance = Zo
Transmission Line
Z1
Vin
C2
die
Adjoining pins
Connector
Controlled Impedance
PCB trace
package
On-Chip
Driving
Source

3. M.H. Perrott MIT OCW
High Speed, Broadband Amplifiers
ƒ The first thing that you typically do to the input signal
is amplify it
ƒ Function
- Boosts signal levels to acceptable values
- Provides reverse isolation
ƒ Key performance parameters
- Gain, bandwidth, noise, linearity
VL
C1 RL
L1
Delay = x
Characteristic Impedance = Zo
Transmission Line
Z1
Vin
C2
die
Adjoining pins
Connector
Controlled Impedance
PCB trace
package
On-Chip
Driving
Source
Amp
Vout

4. M.H. Perrott MIT OCW
Basics of MOS Large Signal Behavior (Qualitative)
S D
G
Cchannel = Cox(VGS-VT)
VGS
VDS=0
S D
G
VGS
VD=∆V
S D
G
VGS
VD>∆V
Triode
Pinch-off
Saturation
VDS
ID
ID
ID
ID
Triode
Pinch-off
Saturation
∆V
Overall I-V Characteristic

5. M.H. Perrott MIT OCW
Basics of MOS Large Signal Behavior (Quantitative)
S D
G
Cchannel = Cox(VGS-VT)
VGS
VDS=0
S D
G
VGS
VD=∆V
S D
G
VGS
VD>∆V
Triode
Pinch-off
Saturation
ID
ID
ID
ID = µnCox
W
L
(VGS - VT - VDS/2)VDS
ID µnCox
W
L
(VGS - VT)VDS
for VDS << VGS - VT
ID = µnCox
W
L
1
2
(VGS-VT)
2
(1+λVDS)
(where λ corresponds to
channel length modulation)
∆V = VGS-VT
∆V =
µnCoxW
2IDL

6. M.H. Perrott MIT OCW
Analysis of Amplifier Behavior
ƒ Typically focus on small signal behavior
- Work with a linearized model such as hybrid-π
- Thevenin modeling techniques allow fast and efficient
analysis
ƒ To do small signal analysis:
RS
RG
RD
vin
vout
Vbias
ID
1) Solve for bias current Id
2) Calculate small signal
parameters (such as gm, ro)
3) Solve for small signal response
using transistor hybrid-π small
signal model
Small Signal Analysis Steps

7. M.H. Perrott MIT OCW
MOS DC Small Signal Model
ƒ Assume transistor in saturation:
ƒ Thevenin modeling based on the above
RS
RG
RD
RD
RS
RG
-gmbvs
vgs
vs
ro
gmvgs
gm = µnCox(W/L)(VGS - VT)(1 + λVDS)
= 2µnCox(W/L)ID (assuming λVDS << 1)
Cox
2qεsNA
2 2|Φp| + VSB
γgm
where γ =
gmb =
In practice: gmb = gm/5 to gm/3
λID
1
ro =
ID

8. M.H. Perrott MIT OCW
Capacitors For MOS Device In Saturation
S D
G
VGS
VD
>∆V
ID
LD
LD
overlap cap: Cov = WLDCox + WCfringe
B
Cgc
Ccb
Cov
Cjdb
Cjsb
Cov
Side View
gate to channel cap: Cgc = CoxW(L-2LD)
channel to bulk cap: Ccb - ignore in this class
S D
Top View
W
E
L
E
E
source to bulk cap: Cjsb =
1 + VSB ΦB
Cj(0)
1 + VSB ΦB
Cjsw(0)
WE + (W + 2E)
junction bottom wall
cap (per area)
junction sidewall
cap (per length)
drain to bulk cap: Cjsd =
1 + VDB ΦB
Cj(0)
1 + VDB ΦB
Cjsw(0)
WE + (W + 2E)
2
3
(make 2W for "4 sided"
perimeter in some cases)
L

9. M.H. Perrott MIT OCW
MOS AC Small Signal Model (Device in Saturation)
RS
RG
RD
RD
RS
RG
-gmbvs
vgs
vs
ro
gmvgs
ID
Csb
Cgs
Cgd
Cdb
Cgs = Cgc + Cov = CoxW(L-2LD) + Cov
2
3
Cgd = Cov
Csb = Cjsb (area + perimeter junction capacitance)
Cdb = Cjdb (area + perimeter junction capacitance)

10. M.H. Perrott MIT OCW
Wiring Parasitics
ƒ Capacitance
- Gate: cap from poly to substrate and metal layers
- Drain and source: cap from metal routing path to
substrate and other metal layers
ƒ Resistance
- Gate: poly gate has resistance (reduced by silicide)
- Drain and source: some resistance in diffusion region,
and from routing long metal lines
ƒ Inductance
- Gate: poly gate has negligible inductance
- Drain and source: becoming an issue for long wires
Extract these parasitics from circuit layout

11. M.H. Perrott MIT OCW
Frequency Performance of a CMOS Device
ƒ Two figures of merit in common use
- ft : frequency for which current gain is unity
- fmax : frequency for which power gain is unity
ƒ Common intuition about ft
- Gain, bandwidth product is conserved
- We will see that MOS devices have an ft that shifts with
bias
ƒ This effect strongly impacts high speed amplifier
topology selection
ƒ We will focus on ft
- Look at pages 70-72 of Tom Lee’s book for discussion
on fmax

12. M.H. Perrott MIT OCW
Derivation of ft for MOS Device in Saturation
ƒ Assumption is that input is current, output of device
is short circuited to a supply voltage
- Note that voltage bias is required at gate
ƒ The calculated value of ft is a function of this bias voltage
-gmbvs
vgs ro
gmvgs
ID+id
Csb
Cgs
Cgd
Cdb
iin
Vbias
RLARGE
id
iin

13. M.H. Perrott MIT OCW
Derivation of ft for MOS Device in Saturation
-gmbvs
vgs ro
gmvgs
ID+id
Csb
Cgs
Cgd
Cdb
iin
Vbias
RLARGE
id
iin

14. M.H. Perrott MIT OCW
Derivation of ft for MOS Device in Saturation
1
id
iin
f
ft
slope = -20 dB/dec

15. M.H. Perrott MIT OCW
Why is ft a Function of Voltage Bias?
ƒ ft is a ratio of gm to gate capacitance
- gm is a function of gate bias, while gate cap is not (so long
as device remains biased)
ƒ First order relationship between gm and gate bias:
- The larger the gate bias, the higher the value for ft
ƒ Alternately, ft is a function of current density
- So ft maximized at max current density (and minimum L)

16. M.H. Perrott MIT OCW
Speed of NMOS Versus PMOS Devices
ƒ NMOS devices have much higher mobility than PMOS
devices (in current, non-strained, bulk CMOS processes)
- Intuition: NMOS devices provide approximately 2.5 x gm
for a given amount of capacitance and gate bias voltage
- Also: NMOS devices provide approximately 2.5 x Id for a
given amount of capacitance and gate bias voltage

17. M.H. Perrott MIT OCW
Assumptions for High Speed Amplifier Analysis
ƒ Assume that amplifier is loaded by an identical
amplifier and by fixed wiring capacitance
ƒ Intrinsic performance
- Defined as the bandwidth achieved for a given gain
when Cfixed is negligible
- Amplifier approaches intrinsic performance as its device
sizes (and current) are increased
ƒ In practice, optimal sizing (and power) of amplifier is
roughly where Cin+Cout = Cfixed
Amp Amp
Cfixed
Cin
Cin
Ctot = Cout+Cin+Cfixed
Cout

18. M.H. Perrott MIT OCW
The Miller Effect
ƒ Concerns impedances that connect from input to
output of an amplifier
ƒ Input impedance:
ƒ Output impedance:
Amp
Zin
Zf
Av
ZL
Vout
Vin
Zout

19. M.H. Perrott MIT OCW
Example: The Impact of Capacitance in Feedback
ƒ Consider Cgd in the MOS device as Cf
- Assume gain is negative
ƒ Impact on input capacitance:
ƒ Output impedance:
Amp
Zin
Av
ZL
Vout
Vin
Zout
Cf

20. M.H. Perrott MIT OCW
Amplifier Example – CMOS Inverter
ƒ Assume that we set Vbias such that the amplifier
nominal output is such that NMOS and PMOS
transistors are all in saturation
- Note: this topology VERY sensitive to bias errors
Cfixed
Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + Cfixed
M2
M1
M4
M3
Miller multiplication factor
Vbias
vin
(+Cov1+Cov2)
vout

21. M.H. Perrott MIT OCW
Transfer Function of CMOS Inverter
Low Bandwidth!
Cfixed
Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + Cfixed
M2
M1
M4
M3
Miller multiplication factor
Vbias
vin
(+Cov1+Cov2)
vout
1
vout
vin
f
slope = -20 dB/dec
(gm1+gm2)(ro1||ro2)
2πCtot(ro1||ro2)
1 gm1+gm2
2πCtot

22. M.H. Perrott MIT OCW
Add Resistive Feedback
Bandwidth
extended and
less sensitivity
to bias offset
Cfixed
Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + CRf /2 + Cfixed
M2
M1
M4
M3
Miller multiplication factor
Vbias
vin
(+Cov1+Cov2)
vout
Rf
1
vout
vin
f
slope = -20 dB/dec
(gm1+gm2)(ro1||ro2)
2πCtot(ro1||ro2)
1 gm1+gm2
2πCtot
(gm1+gm2)Rf
2πCtotRf
1

23. M.H. Perrott MIT OCW
We Can Still Do Better
ƒ We are fundamentally looking for high gm to
capacitance ratio to get the highest bandwidth
- PMOS degrades this ratio
- Gate bias voltage is constrained
Cfixed
Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + CRf /2 + Cfixed
M2
M1
M4
M3
Miller multiplication factor
Vbias
vin
(+Cov1+Cov2)
vout
Rf

24. M.H. Perrott MIT OCW
Take PMOS Out of the Signal Path
ƒ Advantages
- PMOS gate no longer loads the signal
- NMOS device can be biased at a higher voltage
ƒ Issue
- PMOS is not an efficient current provider (Id/drain cap)
ƒ Drain cap close in value to Cgs
- Signal path is loaded by cap of Rf and drain cap of
PMOS
CL
M2
M1
Vbias
vin
vout
Rf
Vbias2
Ibias
CL
M1
Vbias
vin
vout
Rf

25. M.H. Perrott MIT OCW
Shunt-Series Amplifier
ƒ Use resistors to control the bias, gain, and
input/output impedances
- Improves accuracy over process and temp variations
ƒ Issues
- Degeneration of M1 lowers slew rate for large signal
applications (such as limit amps)
- There are better high speed approaches – the advantage
of this one is simply accuracy
Ibias
M1
Vbias
vin
vout
Rf
R1
Rs
RL
Rin Rout
M1
Vbias
vin
vout
Rf
R1
Rs
RL
Rin Rout

26. M.H. Perrott MIT OCW
Shunt-Series Amplifier – Analysis Snapshot
ƒ From Chapter 8 of Tom Lee’s
book (see pp 191-197):
- Gain
- Input resistance
- Output resistance
M1
Vbias
vin
vout
Rf
R1
Rs
RL
Rin Rout
vx
Same for Rs = RL!

27. M.H. Perrott MIT OCW
NMOS Load Amplifier
ƒ Gain set by the relative sizing of M1 and M2
Cfixed
M1
Vbias
vin
vout
M2
gm2
1
1
vout
vin
f
slope =
-20 dB/dec
gm1
2πCtot
gm1
2πCtot
gm2
gm2
Ctot = Cdb1+Csb2+Cgs2 + Cgs3+KCov3 + Cfixed
Miller multiplication factor
(+Cov1)
M3
Vdd
Id

28. M.H. Perrott MIT OCW
Design of NMOS Load Amplifier
ƒ Size transistors for gain and speed
- Choose minimum L for maximum speed
- Choose ratio of W1 to W2 to achieve appropriate gain
ƒ Problem: VT of M2 lowers the bias voltage of the next
stage (thus lowering its achievable ft)
- Severely hampers performance when amplifier is cascaded
- One person solved this issue by increasing Vdd of NMOS
load (see Sackinger et. al., “A 3-GHz 32-dB CMOS Limiting
Amplifier for SONET OC-48 receivers”, JSSC, Dec 2000)
Cfixed
M1
Vbias
vin
vout
M2
gm2
1
Ctot = Cdb1+Csb2+Cgs2 + Cgs3+KCov3 + Cfixed
Miller multiplication factor
(+Cov1)
M3
Vdd
Id

29. M.H. Perrott MIT OCW
Resistor Loaded Amplifier (Unsilicided Poly)
ƒ This is the fastest non-enhanced amplifier I’ve found
- Unsilicided poly is a pretty efficient current provider
(i..e, has a good current to capacitance ratio)
- Output swing can go all the way up to Vdd
ƒ Allows following stage to achieve high ft
- Linear settling behavior (in contrast to NMOS load)
M1
RL
vout
M2
Cfixed
Id
Vbias
vin
Ctot = Cdb1+CRL/2 + Cgs2+KCov2 + Cfixed
Miller multiplication factor
(+Cov1)
1
vout
vin
f
slope =
-20 dB/dec
gm1
2πCtot
gm1RL
2πRLCtot
1
Vdd

30. M.H. Perrott MIT OCW
Implementation of Resistor Loaded Amplifier
ƒ Typically implement using differential pairs
ƒ Benefits
- Self-biased
- Common-mode rejection
ƒ Negative
- More power than single-ended version
M6
M1 M2
M5
αIbias
Vin+
R1
Vin-
R2
Vo+
Vo-
M7
M3 M4
Cfixed Cfixed
Ibias
Ibias/2
Vdd

31. M.H. Perrott MIT OCW
The Issue of Velocity Saturation
ƒ We classically assume that MOS current is calculated as
ƒ Which is really
- Vdsat,l corresponds to the saturation voltage at a given
length, which we often refer to as ∆V
ƒ It may be shown that
- If Vgs-VT approaches LEsat in value, then the top equation is
no longer valid
ƒ We say that the device is in velocity saturation

32. M.H. Perrott MIT OCW
Analytical Device Modeling in Velocity Saturation
ƒ If L small (as in modern devices), than velocity
saturation will impact us for even moderate values
of Vgs-VT
- Current increases linearly with Vgs-VT!
ƒ Transconductance in velocity saturation:
- No longer a function of Vgs!

33. M.H. Perrott MIT OCW
Example: Current Versus Voltage for 0.18µ Device
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
V
gs
(Volts)
I
d
(milliAmps)
Id
versus Vgs
M1
Id
Vgs
W
L
=
1.8µ
0.18µ

34. M.H. Perrott MIT OCW
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
V
gs
(Volts)
g
m
(milliAmps/Volts)
g
m
versus V
gs
Example: Gm Versus Voltage for 0.18µ Device
M1
Id
Vgs
W
L
=
1.8µ
0.18µ

35. M.H. Perrott MIT OCW
0 100 200 300 400 500 600 700
0
0.2
0.4
0.6
0.8
1
Current Density (microAmps/micron)
Transconductance
(milliAmps/Volts)
Transconductance versus Current Density
Example: Gm Versus Current Density for 0.18µ Device
M1
Id
Vgs
W
L
=
1.8µ
0.18µ

36. M.H. Perrott MIT OCW
How Do We Design the Amplifier?
ƒ Highly inaccurate to assume square law behavior
ƒ We will now introduce a numerical procedure based
on the simulated gm curve of a transistor
- A look at gm assuming square law device:
- Observe that if we keep the current density (Id/W)
constant, then gm scales directly with W
ƒ This turns out to be true outside the square-law regime
as well
- We can therefore relate gmof devices with different
widths given that have the same current density

37. M.H. Perrott MIT OCW
A Numerical Design Procedure for Resistor Amp – Step 1
ƒ Two key equations
- Set gain and swing (single-
ended)
ƒ Equate (1) and (2) through R
M6
M1 M2
M5
αIbias
Vin+
R
Vin-
R
Vo+
Vo-
2Ibias
Ibias
Vdd
Can we relate this formula to a gm curve taken
from a device of width Wo?

38. M.H. Perrott MIT OCW
ƒ We now know:
ƒ Substitute (2) into (1)
ƒ The above expression allows us to design the resistor
loaded amp based on the gm curve of a representative
transistor of width Wo!
A Numerical Design Procedure for Resistor Amp – Step 2

39. M.H. Perrott MIT OCW
Example: Design for Swing of 1 V, Gain of 1 and 2
ƒ Assume L=0.18µ, use previous gm plot (Wo=1.8µ)
0 100 200 300 400 500 600 700
0
0.2
0.4
0.6
0.8
1
Current Density - Iden (microAmps/micron)
Transconductance
(milliAmps/Volts)
Transconductance versus Current Density
A=2 A=1
gm(wo=1.8µ,Iden)
ƒ For gain of 1,
current density =
250 µA/µm
ƒ For gain of 2,
current density =
115 µA/µm
ƒ Note that current
density reduced
as gain increases!
- ft effectively
decreased

40. M.H. Perrott MIT OCW
Example (Continued)
ƒ Knowledge of the current density allows us to design
the amplifier
- Recall
- Free parameters are W, Ibias, and R (L assumed to be fixed)
ƒ Given Iden = 115 µA/µm (Swing = 1V, Gain = 2)
- If we choose Ibias = 300 µA
ƒ Note that we could instead choose W or R, and then
calculate the other parameters

41. M.H. Perrott MIT OCW
How Do We Choose Ibias For High Bandwidth?
ƒ As you increase Ibias, the size of transistors also
increases to keep a constant current density
- The size of Cin and Cout increases relative to Cfixed
ƒ To achieve high bandwidth, want to size the devices
(i.e., choose the value for Ibias), such that
- Cin+Cout roughly equal to Cfixed
Amp Amp
Cfixed
Cin
Cin
Ctot = Cout+Cin+Cfixed
Cout