Engineering

1. Engr. Kashif Nisar
Design Engineer (Integrated Circuit Lab),
National Institute of Electronics, Islamabad, Pakistan.
10 years of Experience in Academia and R&D
MS in Electrical Engineering (SoC)
Linkoping University, Sweden
National Institute of Electronics
Ministry of Science & Technology-Islamabad

2. Responsibilities at NIE
Working as a Design Engineer in Integrated Circuit Lab
• Working on Full custom design of 8-bit SAR ADC in 65nm TSMC CMOS technology
• Design of Low power All digital delay locked loop in 65nm TSMC kit
• Design of Binary weighted Capacitive Digital to Analog Converter (CDAC) in 65nm
technology
• Design of Ultra low power dynamic latched comparator in 45nm CMOS technology
• Design of Wide range low power current starved inverter
• Design of Phase detector and lock detector
• Design of 5 bit T-Flip flop based counter design in 65nm CMOS technology
• Currently supervising 10 Engineering Students in Chip Designing
• Provides hands-on on Cadence tools to interns
• Conducted various Trainings, Workshops and Seminars on Cadence IC design tools

3. Responsibilities at Bahria University
• Currently working as a Visiting Lecturer in Computer
Engineering department
• Teaches VLSI design to Computer Engineering Students

4. Responsibilities at University of Lahore
Worked as a Lecturer (Electrical Engineering Department)
• Taught Electrical and Electronics Engineering courses (Integrated circuits,
Semiconductor materials and diodes, Electronic devices and circuits, Power
electronics and Circuit theory) at undergraduate level in Electrical Engineering
department
• Supervised the final year projects
• Performed Lab experiments
• Program Evaluations and worked with accreditation body
• OBE implementations
• Examination duties such as invigilation's and paper checking.

5. MS Thesis (DC to DC Converter)
It’s a buck type DC to DC converter designed for Ultra low power applications
using 65nm CMOS Technology in Cadence Virtuoso)
• Voltage mode Control
• Pulse width modulation (PWM)
technique
• Sizing the switches to a low
parasitic output and gate
capacitances to reduce the
capacitive and gate-drive losses.
• Error amplifier biasing current is
chosen a small value (12.5 μA) to
reduce the power dissipations in
the control loop of the system.

6. Top level design of 8 bit SAR-ADC

7. Implementation of SAR Logic

8. Test bench of D-Flip flop

9. Set-Reset D-Flip flop

10. Simulation results of D-Flip Flop

11. Latch Comparator Schematic

12. Layout of Comparator in Cadence Virtuoso

13. Parasitic Extraction of Comparator

14. Simulation Results of Comparator

15. Delay Locked Loop (DLL) Block Diagram

16. DLL Implementation in Cadence Virtuoso

17. Simulation Results

18. Simulation results (Cont..)

19. Simulation Results (Cont..)

20. 8-bit Counter design using T-Flip Flop

21. Delay Cell

22. Layout of Delay Cell

23. Schematic of Delay Line

24. Layout of Delay Line

25. Schematic of Current Starved Inverter for Delay Cell

26. DLL IC TapeOut

27. Conducted Chip Designing Workshop at NIE

28. Thank You