1. Profile:
2 years industrial experience with focus on Analog Building Blocks like
Amplifiers, Comparators, Current Mirros, Power-Management blocks like Bandgap
References, LDO, Voltage clamp & Thermal Shutdown, Voltage Mode DC DC Buck
loop modelling.
Education:
 Master of Technology (MICRO ELECTRONICS & VLSI)
• National Institute of Technology, Durgapur (2014)
• CGPA : 9.4
 Bachelor of Technology (Electronics & Communication)
• JNTU, Kakinada (2011)
• Percentage : 81
 Intermediate(Maths, Physics, Chemistry)
• Narayana Junior College, Andhra Pradesh (2007)
• Percentage : 95.4
 10th
Class
• Andhra Pradesh State Board (2005)
• Percentage : 85.2
Professional Details:
l Joined Sankalp Semiconductor on July 1st
, 2014 as Circuit Design Engineer
l Undergone training on fundamentals of Analog Design like Comparators, Amplifiers,
Level shifters.
l Worked on power management blocks like Bandgap along with sub-blocks like Under
voltage detection, Thermal Shutdown, Over voltage detection.
l Worked on power management blocks like LDO ,Voltage clamp for LDO
l Worked on transient and average modeling of voltage mode control DC DC Buck
converter
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L Jagadesh Aryasomayajula
arya.jagadeesh@gmail.com
+91-8050727319

2. Projects:
 High PSRR and fast transient Capless LDO
 Description: This includes designing of capless LDO with very sharp transient
response and high PSRR requirement with low bias current.
 Responsibilities:
• Implemented active and bypass modes of operation with good stability margins.
• To ensure the LDO output does not jumps with very fast transients (load/line).
 Challenges:
• To stabilize the loop at zero load.
• Limit the quiescent & leakage currents
• Achieving high PSRR.
 Technology/ Process: 90nm, 3.6V Technology
 Duration of Project: 5 months
 Bandgap Top
 Description: This includes design of Bandgap Core, V2I, Non-Inv Amplifier &
Bandgap sub-blocks like Bandgap Buffer, Under Voltage Detection & Thermal
shutdown.
 Responsibilities:
• To achieve a high accuracy BGAP output with 5 bit trimming.
• Designed Bandgap with low IQ & low noise.
• To achieve a highly accurate IREF with 4 bit trimming.
• Designed and verified under voltage detection(UVD) & thermal shutdown
blocks.
 Challenges:
• Achieve the target BGAP accuracy in spite of large PVT variations & Mismatches
• Biasing V2I, Amplifier with a large Vth variation (~1V)
 Technology/ Process: 90nm, 5V Technology
 Duration of Project: 3 months

3.  Capped LDO
 Description: This includes Designing of Off-chip capacitor LDO with Active &
Low power modes and Inrush protection scheme
 Responsibilities:
• Understanding functionality and various specifications of LDO and Implementing
different architectures
 Challenges:
• Stabilizing the loop of LDO at full load
• Inrush limitation circuit implementation
 Technology/ Process: 180nm,
 Duration of Project: 3.0 month
 Mini - BandGap
 Description: This includes implementing of Bandgap architecture without error
amplifier.
 Responsibilities:
• To achieve the accuracy .
 Challenges:
• Second order compensation for high accuracy
 Technology/ Process: 40nm, 3.3V Technology
 Duration of Project: 2.0 month
 Voltage-Mode Buck DCDC Modeling (Training)
 Description: This includes accurate modeling of the voltage loop.
 Responsibilities:
• Modeled transient and average behavior of DC DC Buck voltage loop .
 Challenges:
• To use appropriate modeling technique and compensation
 Technology/ Process: 40nm, 3.3V Technology
 Duration of Project: 1.0 month

4.  V2I converter with 4-bit trimming
 Description: A high accuracy (variation < 4%), temperature compensated V2I
converter.
 Responsibilities:
• To study and finalize V2I architecture
• Achieved high accuracy output current using 4-bit trimming
 Challenges:
• To achieve temperature compensation in output current
 Technology/ Process: 90nm, 5V Technology
 Duration of Project: 1 month
 Voltage Clamp for LDO
 Description: This block clamps LDO output to a value (+5%) of the steady output.
 Responsibilities:
• Modified the existing architecture to meet the specs
• To run and verify specs across PVT & MC
 Challenges:
• To achieve good stability margins along with the desired (5%) offset.
 Technology/ Process : 90nm, 3.6V Technology
 Duration of Project : 1 month
 40nm Two stage Buffer (Training)
 Description: Design of two stage differential amplifier with wide Bandwidth (8MHz)
 Responsibilities:
• Designed current mirror, 5 pack amplifier followed by CS stage
• Compensation of two stage
• Setting up test-bench and running required simulations
 Challenges:
• Learning the design flow and tools like Nimble, etc.
• Learning 3-Amp structure for biasing & stability analysis
• Achieve 8MHz BW with a quiescent current of 16uA & Achieve +/-4mV offset
 Technology/ Process: 40nm, 1.8V Technology
 Duration of Project: 1.5 month

5.  40nm Fully Differential Amplifier (Training)
 Description: Design of fully differential amplifier with CMFB
 Responsibilities:
• To design fully differential amplifier using Folded cascade architecture
• Implementing CMFB loop to define the output common mode voltage
 Challenges:
• Implementing CMFB loop
• Transient stability of CMFB loop
 Technology/ Process: 40nm, 1.8V Technology
 Duration of Project: 1 month
 Design of a wide band Rail-to-Rail Amplifier (Training)
 Description: Design a wide bandwidth (10MHz) amplifier with common mode close to
rails.
 Responsibilities:
• To choose an appropriate architecture meeting specs.
• Simulated across corners and verified the amplifier operation
• To learn basic parameter extraction like bias margins, phase, gain, bandwidth
etc. through running scripts
 Challenges:
• To achieve biasing margins of the given architecture
• To achieve wide bandwidth with quiescent current of 60uA
 Technology/ Process: 40nm, 1.8V
 Duration of Project: 1.5 months
 CAD Tools
 Virtuoso, Virtuoso Schematic Editor, ADE, Monte Carlo tools
 Hardware Description Languages
 VHDL , Verilog, VerilogA
Personal Details:
Date of Birth : 13/08/1990
Languages Known : English, Hindi, Telugu
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6. Permanent Address : LIG 530 ,13th
cross, Navanagar, Hubli
Karnataka
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7. Permanent Address : LIG 530 ,13th
cross, Navanagar, Hubli
Karnataka
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