Engr. Kashif Nisar has 10 years of experience in academia and research and development. He received an MS in Electrical Engineering from Linkoping University in Sweden. He currently works as a Design Engineer at the National Institute of Electronics in Islamabad, Pakistan, where he designs integrated circuits including an 8-bit SAR ADC, delay locked loop, and 3-6 GHz VCO. Previously, he worked as a Lecturer teaching electrical engineering courses at the University of Lahore. His MS thesis involved designing a buck DC-to-DC converter for ultra-low power applications using 65nm CMOS technology. He has also designed printed circuit boards for applications such as a line power conditioner and control system for a

1. Engr. Kashif Nisar
Design Engineer (Integrated Circuit Lab),
National Institute of Electronics, Islamabad, Pakistan.
10 years of Experience in Academia and R&D
MS in Electrical Engineering (SoC)
Linkoping University, Sweden
National Institute of Electronics
Ministry of Science & Technology-Islamabad

2. Responsibilities at NIE
Working as a Design Engineer in Integrated Circuit Lab
• Works on Full custom design of 8-bit SAR ADC in 65nm
TSMC CMOS technology
• Designed a Full Custom design of Delay Locked Loop
(DLL) in 65nm CMOS technology
• Designed a 3-6 GHz VCO for PLL in 65nm CMOS
technology
• Currently supervising 10 Engineering Students in Chip
Designing
• Conducted various Trainings, Workshops and Seminars
on Cadence IC design tools

3. Responsibilities at University of Lahore
Worked as a Lecturer (Electrical Engineering Department)
• Taught Electrical and Electronics Engineering courses
(Integrated circuits, Semiconductor materials and diodes,
Electronic devices and circuits, Power electronics and Circuit
theory) at undergraduate level in Electrical Engineering
department
• Supervised the final year projects
• Performed Lab experiments
• Program Evaluations and worked with accreditation body
• OBE implementations
• Examination duties such as invigilation's and paper checking.

4. MS Thesis (DC to DC Converter)
It’s a buck type DC to DC converter designed for Ultra low power applications
using 65nm CMOS Technology in Cadence Virtuoso)
• Voltage mode Control
• Pulse width modulation (PWM)
technique
• Sizing the switches to a low
parasitic output and gate
capacitances to reduce the
capacitive and gate-drive losses.
• Error amplifier biasing current is
chosen a small value (12.5 μA) to
reduce the power dissipations in
the control loop of the system.

5. Block Diagram of Successive Approximation
Register Analog to Digital Converter (SAR-ADC)

6. Top level design of 8 bit SAR-ADC

7. Implementation of SAR Logic

8. Test bench of D-Flip flop

9. Set-Reset D-Flip flop

10. Simulation results of D-Flip Flop

11. Latch Comparator Schematic

12. Layout of Comparator in Cadence Virtuoso

13. Parasitic Extraction of Comparator

14. Simulation Results of Comparator

15. Delay Locked Loop (DLL) Block Diagram

16. DLL Implementation in Cadence Virtuoso

17. Simulation Results

18. Simulation results (Cont..)

19. Simulation Results (Cont..)

20. 8-bit Counter design using T-Flip Flop

21. Layout of Counter

22. Combiner in Cadence Virtuoso

23. Layout of Combiner

24. Delay Cell

25. Layout of Delay Cell

26. Schematic of Delay Line

27. Layout of Delay Line

28. Schematic of Current Starved Inverter for Delay Cell

29. DLL IC TapeOut

30. Conducted Chip Designing Workshop at NIE

31. Power Line Conditioner
• Smooth Power Conditioning Unit is being designed and
developed in NIE in order to provide pure sinusoidal
wave with regulated voltage output. Line Conditioner
streamlines voltage fluctuations, frequency
disturbance and harmonics filtration in power line.
• Conditioners specifically work to smooth the sinusoidal
A.C. waveform and maintain a constant voltage over
varying & fluctuating loads.
• This device intended to improve the quality of the
power that is delivered to sensitive and sophisticated
electrical load equipment used in military, strategic
organizations and industry.

32. Printed Circuit board (PCB) of Line Conditioner

33. Top View

34. Bottom View

35. 3-D view of line Conditioner PCB

36. Assembled PCB

37. PCB for Control Shed of Poultry farm

38. Top view

39. Bottom View

40. Reverse Engineering of PCB

41. Thank You