1. KANTETI AMAR
AMSIP Design Engineer
amarkanteti208@gmail.com
Contact: +917506134434
SUMMARY
• Semiconductor professional with more than 1 year experience in Analog and Mixed signal Design.
• Good academic record - M.Tech.in Electronic Systems from IIT Bombay.
• Worked on many challenging blocks Bandgaps,POR,Bootstrap switches and Time interleaved flash
ADCs.
• Worked on technologies 28nm,40nm,65nm,180nm CMOS technologies.
• Experienced in top level extracted simulations of critical analog IPs.
• Worked on Wreal, Vams, Verilog and SMG modelling on various blocks.
• Good experience with AMS tools like ADEXL,Cadence Virtuoso, LayoutXL,Matlab.
• Good understanding of analog circuit design fundamentals.
PROFESSIONAL EXPERIENCE
NXP Semiconductors [jul. 2015 - present]
Analog Mixed Signal IP Design Engineer
• Design of Low power of 0.8 V Bandgap reference in 40nm
– Designed a wide supply (1.1V-3.63V) current summing bandgap for 1uA supply current and 1nA power
down current.
– Provides 1% post trimmed accuracy of 0.2V to 0.8V in steps of 0.1V and 50nA,100nA ZTAT currents.
– Subblocks: 10nA PTAT current source (Beta Multiplier),65dB Cascoded single ended OPAMP, CMOS
Schmitt trigger, Trimming block.
• Design of Low noise of 0.7 V Bandgap reference in 65nm
– Designed a 30uV PTAT current bandgap for a 1.1-2V supply range, 150uA supply current and 15nA
power down current.
– Provides tuning to select 5% accuracy 0.72V to 0.62V at a step of 20mV voltage reference.
– Subblocks: 6uA peaking current source for Bandgap startup, 70dB Folded Cascoded single ended
OPAMP, CMOS Schmitt trigger, Tuning block.
• Design an optimised low power and low area Power On Reset in 40nm
– Designed a 1.2uW POR for a supply range of 1.1-1.32V.
– Provides high tripping point around 0.8V, low tripping point around 0.74V, and hysteresis of 60mV.
– Subblocks: Schmitt Trigger,D Flipflop, AND gate.
• Self proficiency on basic analog blocks,layout, verification and Modelling
– Analysed trade off between Mismatch and area in PMOS and NMOS current mirrors for GO1, GO2
devices in C040nm.
– Certified and completed the course on Nanometer CMOS ICs with 90% conducted by Bits On Chips
at NXP Semiconductors Bangalore in 2015.
– Designed a Telescopic cascoded operational amplifier (OPAMP) in C040nm technology
– Worked on layout of simple differential amplifier and current mirrors using common centroid technique
in C040 technology.
– Trained on Wreal, VAMS and Verilog by Cadence and implemented models for Temperature sensor,
Bandgaps and POR.
– Studied basic working principle of bandgaps, PORs, BODs,Temperature sensors.
– ON GOING: Studying the feedback circuits and implementing DC-DC converter in MATLAB using
simulink.
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2. EDUCATIONAL QUALIFICATIONS
Examination University Institute Year CPI/%
Post Graduation IIT Bombay IIT Bombay 2015 7.64
Undergraduate Specialization: Electronics and Communication Engineering
Graduation GITAM GITAM 2012 8.34
Intermediate/+2 Board of Intermediate Gowtham Junior College 2008 92.9
Matriculation BSEAP ZP High School, Mandavalli 2006 87
PROJECTS AND SEMINAR
• M. Tech. Project: Design a test setup for Metastability charcterization in D FlipFlop
Guide: Prof. Maryam Shojaei Bhagini, IIT Bombay [Jun. 2015]
– Studied different architectures for measuring the Metastability parameters in D flipflop.
– Proposed an analog base approach to detect all the metastable events and calculate parameters with
picosecond resolution.
– Designed a 10GHz Bootsrapped Track and hold, Comparator and D flipflop to measure the metastability
in Synchronizers.
– Met the following specifications: MTBF > 100years with in less measurement time,and Resolution <1ps.
– Futurescope: Observe the effect of load variation and temperature variation on Metastability parame-
ters.
• M. Tech. Seminar: 12.5 GB/S ONCHIP OSCILLOSCOPE TO MEASURE EYE DIAGRAMS
AND JITTER HISTOGRAMS OF HIGH SPEED SIGNALS
Guide: Prof. Maryam Shojaei Bhagini, IIT Bombay [Dec. 2013]
– Proposed architecture able to generate eye diagrams with sub picosecond resolution.
– Consumes a 1mW power and core area is 60X40µ.
• B. Tech. Project: Optimal Recursive Data Pre processing algorithm based channel estimation
for high mobility OFDM systems
Guide: Asst.Prof. CH.RAJASEKHAR, GITAM University [April 2013]
– Developed MATLAB code for MSEE analysis for different Doppler speeds of OFDM receiver and
estimating the CE-BEM channel coefficients using proposed algorithm.
– Obtained the MSEE of OFDM receiver of our proposed scheme 10 times better than traditional CT
based scheme.
– Further improve the MSEE by transferring more CP bits to extract the CSI information accurately and
eliminate residue ICI.
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3. COURSE WORK
• CMOS Analog VLSI Design • RF Microelectronics Chip Design
• VLSI Design LAB • Mixed-signal VLSI Design
• Embedded System Design • System Design
• VLSI Design • Digital Signal Processing
• Electronic System Design • Sensors in Instrumentation
COURSE PROJECTS
• Design of RF Reciever at 1.505GHz frequency [May 2014]
◦ Designed Weaver’s architecture based Reciever for 40dB gain, 2.5dB Noise figure, -10dBm IIP3.
◦ Inductive source degenerated common source amplifier is designed at front end for perfect matching.
◦ Image Rejection is achieved by two stage Direct Down Conversion mixing.
•Navigation System for Visually Impaired Person [April. 2014]
◦ Implemented a Navigation aid for blind person which detects obstracles and sudden variations in his path.
◦ Implemented using ATMEGA16L microcontroller and ultrasonic transceivers.
◦ Gives different kinds of alerts for different situations.
• Design of 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC [May 2014]
◦ Designed Flash ADC using Boot strapped track/hold,dynamic comparator and ROM encoder.
◦ 60dB SNDR is achieved for boot strapped track and hold circuit.
◦ Maximum energy dissipation 1pJ/conversion step and 20dB SNDR of ADC is achieved.
• Design of Switched Capacitor Notch filter with Variable centre frequency [April 2014]
◦ Fifth order Biquad filter is designed to get 40dB rejection at centre frequency.
◦ Designed for 20Hz-3dB bandwidth and Maximum pass band ripple 0.5dB.
◦ High gain and low output impedance two stage OP-AMP is designed for filter .
• Designed a Virtual Channel Router for 4x4 NoC [April. 2014]
◦ Implemented a router using Dimension Order Routing and Round Robin policy for switch allotment.
◦ Implemented 2 virtual channels per router to avoid Dead loack condition.
◦ Synthesized the Verilog design and performed post synthesis simulations.
•Designed a Optimized Average waiting time Lift Group Control System (LGCS) [Feb. 2014]
◦ Implemented a Lift controller system for 3 lifts in a 6 floor building with Emergency button.
◦ Hardware description and testbench is written in VHDL and synthesized using modelsim.
• Designed a Two stage Operational Transconductance Amplifier [Dec. 2013]
◦ Designed a two stage cascode OTA for open loop gain 70dB and Phase Margin 72deg .
◦ Equivalent input rms noise is less than 5µV for 10KHz bandwidth.
SOFTWARE SKILL SET
• Circuit Simulators : Cadence-Spectre, Cadence-Virtuoso
• Hardware Description Languages: VHDL, Verilog, System C
• Tools/Softwares : Modelsim, MATLAB, NGSPICE, LabVIEW,Keil,Magic
• Programming : C, C++
• Embedded Platforms : 8085, 8051,ARM Processor
• Operating Systems : Windows, Linux
INDUSTRIAL TRAINING
Electronics Corporation of India Limited(ECIL),Hyderabad [May 2011- June 2011]
• 30 Days Trained on Automation of HF transceiver testing in Communication Division.
• Got exposure on problems involved in practically implementing and testing of HF transceivers.
POSITIONS OF RESPONSIBILITY
◦ Training interns on the Basic Analog Circuit design in NXP Semiconductors [ONGOING]
◦ Assisted the Undergraduate students in performing experiments in lab sessions for Experimental and Measure-
ment Laboratory as TA in IIT Bombay IC211 [April 2014]
◦ Organizing tutorials and evaluating assignements for Introduction to Electrical and Electronics circuits course
as TA in IIT Bombay. [April 2015]
HOBBIES AND INTERESTS
◦ Playing table tennis, chess.
◦ Writing stories and poets in Telugu
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