Example Report VLSI

Lakehead University
Department of Electrical Engineering
Engi – 4054 Digital VLSI Circuit Design
Final Project
Team Members:
Jonathan Dayus (0573175)
Signature: (Refer to Physical Copy)
Drew Ferguson (0561677)
Signature: Refer to Physical Copy)
Group: 23
Instructor: Dr. Yushi Zhou
Submission Date: Dec 11, 2016

4054 Digital VLSI Circuit Design -- Final Project Dayus & Ferguson
i
Abstract:
The purpose of this project was to familiarize students with the tools and procedures used to
create digital VLSI systems. ModelSim was used as the integrated development environment
(IDE) with Verilog as the hardware description language (HDL) to program the system. Both
structural and behavioural coding methods are investigated and implemented into the project.
The project was created to perform multiple functions, each in its own module where they are all
assimilated using a top module and tested within a test bench. Synchronization for both the
inputs and outputs is implemented by the introduction of edge sensitive devices. Analysis of the
system was accomplished by implementing a test bench. This was where user determined
values are injected into the system. The results are simulated by ModelSim and output into a
timing diagram where the correct values are confirmed. No major problems occurred while
developing the project. The desired and outlined operations were successfully implemented and
tested.

ii
Table of Contents
Abstract:.................................................................................................................................... i
List of Figures:.........................................................................................................................iii
List of Tables:...........................................................................................................................iv
Design Specifications:............................................................................................................. 1
Theory:...................................................................................................................................... 2
Boolean:................................................................................................................................. 2
Structural and Behavioral Coding: .......................................................................................... 2
Add and Shift:......................................................................................................................... 3
Data Flip Flop (DFF):.............................................................................................................. 4
Multiplexer (MUX):.................................................................................................................. 5
HI-Impedance Output Tri-State Buffer: ................................................................................... 5
Design:...................................................................................................................................... 6
Pin Out & Block Diagram:....................................................................................................... 6
Structures:.............................................................................................................................. 8
Common Structures: ........................................................................................................... 9
And Module:.......................................................................................................................11
Or Module:.........................................................................................................................12
Half & Full Adder Modules: ................................................................................................13
Multiplication Module: ........................................................................................................13
Addition Module: ................................................................................................................14
Implementation: ......................................................................................................................16
Files Created:........................................................................................................................16
Hierarchy:..............................................................................................................................17
Simulation Platform: ..............................................................................................................18
Verification:.............................................................................................................................19
Test Vectors: .........................................................................................................................19
Comparison Expected Vs. Simulated: ...................................................................................19
Multiplier Testing Results: ..................................................................................................19
Addition Testing Results: ...................................................................................................21
‘AND’ Testing Results: .......................................................................................................22
‘OR’ Testing Results: .........................................................................................................23
Summary: ................................................................................................................................24
APPENDIX A............................................................................................................................25
Top Module Source Code:.....................................................................................................25
Half Adder Module Source Code: ..........................................................................................26
Full Adder Module Source Code:...........................................................................................27
‘And’ Module Source Code:...................................................................................................28
Multiplier Module Source Code:.............................................................................................30
‘Or’ Module Source Code: .....................................................................................................32
Test Bench Source Code:......................................................................................................34
APPENDIX B............................................................................................................................38
References: .............................................................................................................................39

iii
List of Figures:
Figure 1- Gate Examples ........................................................................................................... 2
Figure 2 - 3 Bit Multiplication...................................................................................................... 3
Figure 3 - Multiplication Example ............................................................................................... 4
Figure 4 - DFF Symbol............................................................................................................... 4
Figure 5 - MUX Symbol.............................................................................................................. 5
Figure 6 – Tri-State Buffer Symbol............................................................................................. 5
Figure 7 - Pin Out & Symbol of ALU........................................................................................... 6
Figure 8 - Block Diagram ........................................................................................................... 7
Figure 9 - General Representation of the Project ....................................................................... 8
Figure 10 - De-Multiplexer Operations ....................................................................................... 9
Figure 11 - D-Flip Flop Structure Overview ...............................................................................10
Figure 12 - The Expected Results Timing Diagram ...................................................................10
Figure 13 - Tri-State Buffer Operations and Structure ...............................................................11
Figure 14 - The Structural Logic of The And_Project Module ....................................................11
Figure 15 - The Structural Logic of The And_Project Module ....................................................12
Figure 16 - Half Adder Structure ...............................................................................................13
Figure 17 - Full Adder Structure................................................................................................13
Figure 18 - Mathematical Procedure for Multiplication Module ..................................................14
Figure 19 - Multiplication Module Arithmetic Structure...............................................................14
Figure 20 - General Structure of the Addition Module................................................................15
Figure 21 - Addition Module Example Calculation.....................................................................15
Figure 22 - Verilog Program Hierarchy......................................................................................17
Figure 23 - ModelSim Display of The Hierarchy ........................................................................18
Figure 24 - Multiplication Test Setup.........................................................................................19
Figure 25 - Simulated Test Results for Multiplier.......................................................................20
Figure 26 - Addition Test Setup.................................................................................................21
Figure 27 - Simulated Test Results for 4 -Bit Adder ..................................................................21
Figure 28 - 'AND’ Test Setup ....................................................................................................22
Figure 29 - Simulated Test Results for ‘And’ Module.................................................................22
Figure 30 - OR Test Setup ........................................................................................................23
Figure 31 - Simulated Test Results for ‘Or’ Module ...................................................................23

iv
List of Tables:
Table 1 - ALU Operation ............................................................................................................ 1
Table 2 - Truth Table for DFF..................................................................................................... 4
Table 3 - Truth Table for MUX.................................................................................................... 5
Table 4 - Truth Table for Tri-State Buffer.................................................................................... 5
Table 5 - Example Truth for One Input ‘and’ Gate.....................................................................12
Table 6 - Example Truth for One Input ‘or’ Gate........................................................................12

1
Design Specifications:
The Arithmetic Logic Unit (ALU) was designed having two, four-bit inputs (A [3:0] and B [3:0])
that were to be used for one of four operations. The project operates each of the modules
corresponding to a two-bit selection input (ALU_OP [1:0]) displayed in table 1. The arithmetic
operations are: bit-wise ‘or’, ‘and’, ‘addition’ and ‘multiplication’. These functions cause the unit
to have an eight-bit output (Dout [7:0]) with a single bit carry out (Cout). The ALU will be a
synchronized system where the inputs and outputs are synchronized with respect to the same
clock signal.
Operation ALU_OP Operation Performed
AND(bitwise) 00 Dout = A&B
OR(bitwise) 01 Dout = A|B
ADDITION 10 Dout = A+B
MULTIPLICATION 11 Dout = A*B
Table 1 - ALU Operation
The ‘and’, ‘or’, and ‘addition’ operations are implemented with structural logic, whereas the
‘multiplication’ operation was implemented by utilizing the add and shift technique. The ‘and’,
‘or’, and ‘addition’ functions will only use the first four bits of the output (Dout). With the
exception of the ‘addition’ function, which will contain an extra Cout bit. The Multiplication
module is the only function that will use the entire eight-bit output.

2
Theory:
This section of the report will explain the basic theoretical concepts used to implement the ALU
operations.
Boolean:
An understanding of Boolean logic was required to complete this project. Boolean functions are
the basic building blocks for digital systems and both structural and behavioural coding demand
this knowledge. For structural coding, logic gates will be built directly from the gate modules
designed by ModelSim software. When logic gates are used in behavioural coding, Boolean
functions can be used as comparators or to implement a larger bitwise ‘and’ and ‘or’ operations.
Used here in behavioural coding, the command would be implementing a larger system rather
than a single logic gate as it is in structural. The basic logic functions that may be implemented
are displayed in figure 1. This project’s Boolean functions are only coded with structural logic.
Structural and Behavioral Coding:
While designing and building this project it is effective to understand how the code will be
translated into hardware. There are two main types of coding in Verilog which are structural and
behavioural. Structural has a more direct representation as to what will be built. It is harder to
use but also harder to understand. This is why behavioural is preferred as it cuts time and costs
on a project. The downside to behavioural is that not all statements are synthesizable and it can
easily introduce redundant hardware. For more complete control over what logic circuits will be
built, structural coding techniques should be used.
Figure 1- Gate Examples

3
Add and Shift:
For the multiplier module the behavioural assignment of ‘ * ’ as a multiplier must be avoided in
this project. Instead, the add and shift method must be used. The multiplication process is
observed in figure 2, and was accomplished by logically ‘anding’ bits together and then adding
these combined values in each of these three rows.
In each row, there will be a constant multiplier to each of the opposite group of bits. In this case
the constant is the B bit, which is being multiplied or ‘and’ operated together by all A bits. Seen
in the first addition B0 was multiplied by A0, A1 & A2. This means if B0=1 there will be an
addition (A2 A1 A0) as a word to the following two lines. If B0=0 then there will be an addition of
(0 0 0) to the following additions. The second line is where the shift was first encountered. The
multiplication by two will shift a binary number by one spot left. Now if B1= 1 this would be the
decimal value of two and would shift that line left one. B1 is also one left of the least significant
digit which is why these are shifted. If B1=1 then the three bits of A0, A1, & A2 are ‘anded’
together but must shift the word one left which looks like (A2 A1 A0 0). Else if B1=0 then the
following line would be (0 0 0 0) which is added to the initial B0 word. The third line is multiplied
by B2. If B2 =1 then that is multiplied by four (or 2*2=4) meaning it would shift left by two. B2
again, is the second bit from the least significant bit corresponding to two shifts left. When B2=1
the addition of (A2 A1 A0 0 0) to the previous words or if B2= 0 then (0 0 0 0 0) will be the
resultant from the previous two addition. The example B=3’b101 shows the addition process in
figure 3.
Figure 2 - 3 Bit Multiplication

4
Data Flip Flop (DFF):
A DFF is a device that will pass the D input to the Q output on a pulse edge triggered event. It
will then hold the output at a constant value for the duration of the pulse. What triggers a DFF is
an edge transition. It can be a positive edge, negative edge or both. A DFF is considered as
sequential logic.
CLK D Q Action
0 1 0 Start
Rise 1 1 Store 1
0 0 1 Hold 1
Rise 0 1 Store 0
Table 2 - Truth Table for DFFFigure 4 - DFF Symbol
Figure 3 - Multiplication Example

5
Multiplexer (MUX):
A MUX is a device that takes multiple inputs and will select which one to pass through to the
output. This device is level sensitive and is considered as combinational logic. Table 3
describes the selection logic of the inputs.
HI-Impedance Output Tri-State Buffer:
In cases where there is a shared output bus, there must be a buffer to protect the circuit from
shorting together. This is where a Tri-State Buffer is used. A tri-state buffer implements a high
impedance to the output until the device is selected where it will pass the signal connected.
S OUT
0 In 1
1 In 2
Table 3 - Truth Table for MUX
Enable Input Output
0 0 z
0 1 z
1 0 0
1 1 1
Table 4 - Truth Table for Tri-State Buffer
Figure 5 - MUX Symbol
Figure 6 – Tri-State Buffer Symbol

6
Design:
This section of the report describes the design process and overview of the ALU device.
Pin Out & Block Diagram:
The following section will describe the architecture of the ALU. This device will consist of two 4-
bit inputs (A and B) and a 2-bit control signal (ALU_OP). The device will also require the input of
a clock signal (CLK) to synchronize the input and the outputs on the rising edge. The control of
these internal operations will be accomplished with reset (rst_n) and enable (EN_Bit) bits. There
will be two outputs from the device, an 8-bit data out (Dout) and a carry bit (Cout).
The pin out and the symbol of the ALU are displayed in figure 7. Multiple wire connections to the
A and B input are required for the 4-bit signals. The selection bits also require multiple data
signals. The output data is a combination of an 8-bit signal coming from the ALU device.
Figure 7 - Pin Out & Symbol of ALU

7
Figure 8 - Block Diagram
Figure 8 displays the layers of the modules used in the ALU. These modules are a combination
of standard modules created by ModelSim software and custom ones. The top module runs the
four custom modules made for arithmetic operations. These functions are only operated if the
selection and enable bits have been implemented correctly. Inside the arithmetic modules are
sub-modules for ‘and’, ‘or’, and ‘xor’ which are all standard modules provided by the ModelSim

8
software. The “halfadder_Project” and “fulladder_Project” modules were created for the addition
arithmetic operation. The block diagram shows the frequency in which the modules are used by
incrementing the “inst” connected to each sub-module name. The multiplication operation does
not use structural architecture to run the module, thus has no sub-modules. The theoretical
structure of the multiplication layer will be explained in the structure sub-section of the report.
Appendix B shows an alternate block diagram with the connections to the top layer.
Structures:
This section will explore the structural logic of all modules created for this project. The four
arithmetic operations connected by the top layer of the projected will be broken down into their
further submodules and explained. Figure 9 shows the general overview of the submodule
connections to the top layer of the project.
Figure 9 - General Representation of the Project

9
Common Structures:
In each of the arithmetic operations connected to the top layer two de-multiplexers are used to
select which operation will receive the input signals (A/B). Figure 10, shows the connection
points of these de-multiplexers along with a truth table. The select bits will either enable the
operation or prevent the signal from passing. This allows for only one arithmetic module to
operate at a time, thus saving power.
Figure 10 - De-Multiplexer Operations
D-Flip Flops are connected to all inputs and outputs of each of the arithmetic operations. This
synchronizes these signals on the rising edge of the clock pulse. Figure 11, shows the structure
of the DFF. By connecting these devices to the inputs and outputs of each arithmetic operation,
there will be a delay of one clock signal from input to output. The reset bit allows for the
synchronized inputs and outputs to be set to logic level low. The enable bit prevents the logic
from being passed on. This analysis is also displayed in the expected timing diagram in figure
12. Figure 11 displays the structural logic of this device with EN_Bit and Rst_n connection
points.

10
Figure 11 - D-Flip Flop Structure Overview
Figure 12 - The Expected Results Timing Diagram
The Tri-state buffer allows for all the common outputs of the arithmetic operations to be
connected together. The buffer is enabled by the select and the enable bits, this allows output to
proceed to the top layer. Otherwise the output presents a high impedance signal stopping
electrons on the common bus from flowing to or from arithmetic operations not in use. Figure
13, displays the symbol and operations of this buffer along with the truth table.

11
Figure 13 - Tri-State Buffer Operations and Structure
And Module:
This submodule performs an ‘and’ operation to both the input signals (A,B). Figure 14 shows the
connection points of the common structures to the four paralleled ‘and’ logic gates. Each of the
‘and’ gates handles one bit from each of the inputs ‘A’ and ‘B’. The results are then
synchronized to output. The following truth table 5 shows the expected output from this
operation. Only when the same synchronized input bits are true will the respective output be
also true.
Figure 14 - The Structural Logic of The And_Project Module

12
Table 5 - Example Truth for One Input ‘and’ Gate
Or Module:
The 4-input ‘or’ submodule operates similar to the ‘and’ module. Instead of the ‘and’ gates, ‘or’
gates are paralleled. Figure 15 shows the structure logic and table 6 displays the truth table for
this operation.
Figure 15 - The Structural Logic of The And_Project Module
Table 6 - Example Truth for One Input ‘or’ Gate

13
Half & Full Adder Modules:
The half and fuller adder modules are used for both the addition of individual bits and in the
multiplication process. Figure 16 shows the structural logic for the half adder. As displayed the
half adder’s carry out is only true when both inputs are high. When only one input is true then
the summation result is also true or logic level high.
Figure 16 - Half Adder Structure
Figure 17 shows the structural logic of the full adder. Now when both inputs are high or one
input is high and the carry in bit is high results in the carry out bit also being high. Summation bit
is only triggered when carry in is high and both inputs are low or when carry in is low and one of
the inputs is high.
Figure 17 - Full Adder Structure
Multiplication Module:
The multiplication module takes the two 4-bit inputs and results in an 8-bit output (Pout). The
mathematical procedure used to perform this calculation is displayed in figure 18. Each input bit
values are represented by number attached to the variable name. To perform the multiplication
of bits the ‘and’ operation is used. To perform the addition of the bit’s half and full adders are
used. The full structure of the multiplication module can be seen in figure 19. This module also
contains the methods for synchronization of the inputs and outputs which are the same as the
previous modules. The de-multiplexer and tri-state buffer are also connected to the inputs and
output respectively, however it is not displayed in the structure diagram.

14
Figure 18 - Mathematical Procedure for Multiplication Module
Figure 19 - Multiplication Module Arithmetic Structure
Addition Module:
The addition module again uses the same methods for synchronization and arithmetic operation
selection as the previous modules. Figure 20 displays the block diagram for the connections to
the half and full adder modules that form the addition module. The first block used the half adder
module because no previous carry bits are required to add the least significant bits. Conversely
the following blocks used full adders to deal with the carry bits from the previous stages. The
functionality of the half and full adders where previously explained.

15
Figure 20 - General Structure of the Addition Module
Figure 20 illustrates an example calculation of A = 5 and B =7 in the addition module.
1. In Module halfadd1, the least significant bits are logically ‘xor’ together to get
Sum_Add[0] = 0 then logically ‘and’ together to get Cout1 = 1.
2. In the fulladd1 block, input B_Sync_Add[1] =1 which is ‘xor’ with the carry in bit from the
previous stage resulting in Sum_Add[1] = 0 and Cout2=1.
3. In the module fulladd2 all inputs are true and the carry in bit is true therefore
Sum_Add[2] = 1 and Cout3 =1.
4. Finally both inputs are false however the carry bit is true in module fulladd3 which results
in Sum_Add[3] = 1 and Cout=0.
Figure 21 - Addition Module Example Calculation

16
Implementation:
This section of the report will cover all the Verilog files created, hierarchy of the modules, and
the simulation platform.
Files Created:
The following are all the file names created for this ALU device. View Appendix A for all source
coding details.
1. Project_TopLayer.v
2. And_Project.v
3. Or_Project.v
4. Addition_Project.v
5. Multiplier_Project.v
6. halfadd_Project.v
7. fulladd_Project.v
8. Final_Project_tb.v
The toplayer module was implemented last because it uses the structural logic of the arithmetic
modules implemented prior. The toplayer only contains wire connections and the arithmetic
modules. The ‘and’ and ‘or’ modules used the predefined structures created by ModelSim to
implement the proper logic. Two submodules were created to implement the addition module
the “halfadd” and the “fulladd”. The halfadd used predefined ‘xor’ and ‘and’ modules to develop
the structure of the half adder. Likewise the fulladd used ‘xor’, ‘and’, and ‘or’ functions to
implement its proper logic. The addition module connected this halfadd and 3 times of the
fulladd modules together to form its overall structure. The Multiplication module was
implemented using a ‘case’ structure with shifting logic and addition. Synchronization of the
input and output variables was accomplished by adding ‘always’ statements and triggering them
on the positive edge of the clock. The tri-state buffers were created by setting the outputs to
high impedance when the enable and select bits were not selected.

17
Hierarchy:
The hierarchy shows how all of the modules and submodules are interconnected, this is
displayed in figure 22. The top module (Project_TopLayer) is connected to all the arithmetic
modules and each is only accessed once. Each of the submodules used further submodules
with the exception of the multiplication process. The “fulladder” operations used the same
submodules and this repetition shown with three dots.
Figure 22 - Verilog Program Hierarchy
Figure 23 shows the hierarchical structure developed in ModelSim’s simulation analysis. The
final submodules or logic level gates in this figure are referred to as processes. The ‘always’
statements used to create the DFFs, DEMUX, and Tri-state buffers are also referred to as
processes. These processes are predefined structures created by ModelSim.

18
Figure 23 - ModelSim Display of The Hierarchy
Simulation Platform:
The initial simulation platform included test benches for each of the submodules to test their
functionality before combining them to the higher layer modules. Once the functionality of each
submodule was confirmed a test bench for the entire project was created.
The final test bench for the project was designed to test the following parameters:
1. The correct selection of each arithmetic module via the select bits.
2. Synchronization of inputs and outputs.
3. The reset input.
4. The enable input.
5. Enabling high impedance on the output.
6. The overall functionality of each of the arithmetic operations.

19
Verification:
This section of the report will cover the testing vectors along with the comparison of the
simulated results to the expected values.
Test Vectors:
The test vectors are the inputs provided to the system in order to test its functionality. The test
vectors common to all arithmetic modules are the following:
1. CLK (Clock signal) = 10ns ON/OFF, total time per cycle = 20ns
2. Rst_n (Reset signal), Active on low.
3. EN_Bit (Enable bit), turns system on/off.
4. ALU_OP (ALU select bits), selects the operation.
5. A,B (Input signals to top layer).
The test bench used for this simulation is provided in Appendix A. The clock used for this
simulation is initially set to zero and operates at a 50% duty cycle. The EN_Bit is initially set low
then held high for the duration of the test to allow the device to operate. Finally the initialization
of each individual arithmetic operation is performed.
Comparison Expected Vs. Simulated:
This section of the report explains the expected results and compares them to the simulated.
Multiplier Testing Results:
The following figure 24 shows how the inputs A and B are changed in the test bench. The
expected results for these operations are also displayed in the comments of the code.
Figure 24 - Multiplication Test Setup

20
Figure 25 displays the simulation timing diagram from the multiplication test. At the beginning of
the test the inputs (A_sync_Mul and B_sync_Mul) and the output (Pout) are reset to zero. This
confirms the Rst_n variable performs as expected. The synchronization process is confirmed by
observing the positive edge of the clock pulse and comparing it to the inputs and the output. The
Pout variable has been delayed by one clock cycle due to the DFFs. This confirms expectations
discussed in the Structural Design section of the report. The overall functionality of the multiplier
is confirmed by converting the hexadecimal values of the Pout and comparing them to expected
results. These conversion and test results are summarized below. The tri-state buffer
functionality was confirmed when the ALU_OP selector bits changed states and the high
impedance was shown as Pout = 8’hZZ. The synchronized input signals also remain zeroed
when the ALU_OP was changed. This indicates that the multiplier operation is no longer
accepting inputs, and the output rejects all other operations signals.
Figure 25 - Simulated Test Results for Multiplier
Summary of the Multiplication Functionality Test:
(A_sync_Mul = 1) X (B_sync_Mul = 1) = (Pout = 8’h01 = 1)
(A_sync_Mul = 3) X (B_sync_Mul = 3) = (Pout = 8’hE1 = 255)

21
Addition Testing Results:
Figure 26 shows the change in the input variables to the addition function. This figure also
shows the expected results from the addition operations in the comments of the code.
Figure 26 - Addition Test Setup
Figure 27 displays the simulation timing diagram. The reset, synchronization, high impedance,
and enable functions of the module were confirmed the same way as the multiplication module.
The addition operation was confirmed by comparing the simulated results from the timing
diagram to the expect results. A summary of this comparison was completed below. The carry
out bit only goes high for any addition past the summation of 15, therefore was only present in
the last addition process.
Figure 27 - Simulated Test Results for 4 -Bit Adder
Summary of the Addition Functionality Test:
(A_sync_Add = 1) + (B_sync_Add = 1) = (Sum_Add = 8’h02 = 2)
(A_sync_Add = 7) + (B_sync_Add = 7) = (Sum_Add = 8’he = 14)
(A_sync_Add = 15) + (B_sync_Add = 15) = (Sum_Add = 8’h04 = 4) and Cout_Add = 1

22
‘AND’ Testing Results:
Figure 28 shows the expected results and test setup for the ‘And’ Module. Each of the four ‘and’
gates are enabled by setting both synchronized input bits high.
Figure 28 - 'AND’ Test Setup
Figure 29 displays the timing diagram for the ‘and’ module and confirms the functionality of this
operation. These results are also consistent with truth table 5 previously displayed in the Design
section of the report.
Figure 29 - Simulated Test Results for ‘And’ Module

23
‘OR’ Testing Results:
Figure 30 displays the test setup and expected results for the ‘Or’ module testing. Similar to the
‘and’ test each of the gates will be activated and shut off.
Figure 30 - OR Test Setup
Figure 31 displays the timing diagram from the test setup. Each of the gates are verified by
observing the output (Dout_Or) and comparing it to the expected results.
Figure 31 - Simulated Test Results for ‘Or’ Module

24
Summary:
The project successfully operates as intended. After testing, all of the individual modules work
on their own as well as combined in the top layer. The project was much more involved than
what was needed because of the structural coding used. This and the fact that it was a relatively
small project means that using behavioural code would be beneficial to reduce time and
complexity of the project. Timing was not thoroughly investigated. An analysis on the parasitic
and contamination delay needed to be performed in order to fully explore the speed limitations
of the project. The input signal could be combined to one pin using a series to parallel
conversion. Likewise, the output signals could be combined using parallel to series conversion.
All the ALU functions were built within structural coding, this means that they will be very precise
and can be easily implemented as building blocks for larger projects. Either the individual
modules could be implemented into another project, or the ALU could be inserted into an
application which requires up to four bit ‘or’, ‘and’, ‘addition’, and ‘multiplication’ operations.
When using this ALU it must be remembered that only one function at a time can be used. If
multiple operations are to be used, they must be performed using sequential pipelining or
another ALU needs to be implemented in order to compute concurrently. It is also important to
note that the multiplication function is unsigned. To implement signed multiplication the
instructions would have to be modified and subsequently the hardware would change.

25
APPENDIX A
Top Module Source Code:

26
Half Adder Module Source Code:

27
Full Adder Module Source Code:

28
‘And’ Module Source Code:

29

30
Multiplier Module Source Code:

31

32
‘Or’ Module Source Code:

33

34
Test Bench Source Code:

35

36

37

38
APPENDIX B

39
References:
[1]N. Weste and D. Harris, CMOS VLSI Design - A Circuit and System Persective, 4th ed.
Boston: Pearson Education, 2011.
[2]"DFF", En.wikipedia.org, 2016. [Online]. Available: https://en.wikipedia.org/wiki/DFF.
[Accessed: 27- Nov- 2016].
[3]"Multiplexer", En.wikipedia.org, 2016. [Online]. Available:
https://en.wikipedia.org/wiki/Multiplexer. [Accessed: 27- Nov- 2016].
[4] Lee, "Vector Boolean Algebra and Calculus", IEEE Transactions on Computers, vol. -25, no.
9, pp. 865-874, 1976.
[5]"Verilog® quickstart", Computers & Mathematics with Applications, vol. 35, no. 5, p. 133,
1998.
[6]"What's a Tri-state Buffer?", Cs.umd.edu, 2016. [Online]. Available:
https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/CompOrg/tristate.html. [Accessed: 27-
Nov- 2016].
[7]D. Chen, "ECE 425 - Intro to VLSI System Design", Courses.engr.illinois.edu, 2016. [Online].
Available: https://courses.engr.illinois.edu/ece425/. [Accessed: 28- Nov- 2016].
[8]"Demultiplexer(Demux)", Electronics Hub, 2016. [Online]. Available:
http://www.electronicshub.org/demultiplexerdemux/. [Accessed: 28- Nov- 2016].
[9]"Monostables", Learnabout-electronics.org, 2016. [Online]. Available: http://www.learnabout-
electronics.org/Digital/dig55.php. [Accessed: 28- Nov- 2016].

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