DRESD Project Presentation - December 2006

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DRESD Project Presentation - December 2006

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DRESD Project Presentation - December 2006

  1. 1. D ynamic R econfigurability in E mbedded S ystem D esign Project Presentation DRESD @ PdM – September 2006
  2. 2. Outline <ul><li>Introduction </li></ul><ul><ul><li>MicroLAB </li></ul></ul><ul><ul><li>DRESD </li></ul></ul><ul><ul><ul><li>Philosophy </li></ul></ul></ul><ul><ul><ul><li>Team and meeting </li></ul></ul></ul><ul><ul><ul><li>Web </li></ul></ul></ul><ul><ul><ul><li>Results </li></ul></ul></ul><ul><ul><ul><li>In the world </li></ul></ul></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Basic principles </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><li>Reconfiguration @ PdM: DRESD </li></ul><ul><ul><li>Earendil flow </li></ul></ul><ul><ul><ul><li>DRESD-HLR </li></ul></ul></ul><ul><ul><ul><li>DRESD-BE </li></ul></ul></ul><ul><ul><li>DRESD Project examples </li></ul></ul><ul><li>Questions? </li></ul>
  3. 3. What’s next <ul><li>Introduction </li></ul><ul><ul><li>MicroLAB </li></ul></ul><ul><ul><li>DRESD </li></ul></ul><ul><ul><ul><li>Philosophy </li></ul></ul></ul><ul><ul><ul><li>Team and meeting </li></ul></ul></ul><ul><ul><ul><li>Web </li></ul></ul></ul><ul><ul><ul><li>Results </li></ul></ul></ul><ul><ul><ul><li>In the world </li></ul></ul></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Basic principles </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><li>Reconfiguration @ PdM: DRESD </li></ul><ul><ul><li>Earendil flow </li></ul></ul><ul><ul><ul><li>DRESD-HLR </li></ul></ul></ul><ul><ul><ul><li>DRESD-BE </li></ul></ul></ul><ul><ul><li>DRESD Project examples </li></ul></ul><ul><li>Questions? </li></ul>
  4. 4. <ul><li>MicroLAB organization: </li></ul><ul><ul><li>Thesis works: 50-60 /year </li></ul></ul><ul><ul><li>Class Projects: 80-100 /year </li></ul></ul><ul><ul><li>PhD students: 8 </li></ul></ul><ul><ul><li>Researchers: 4 </li></ul></ul><ul><ul><li>Professors: 8 </li></ul></ul><ul><li>MicroLAB Workstations: </li></ul><ul><ul><li>Linux: 26 </li></ul></ul><ul><ul><li>Windows: 3 </li></ul></ul><ul><ul><li>Laptop (Linux/Win): 20 </li></ul></ul><ul><ul><li>SUN: 15 </li></ul></ul>MicroLAB
  5. 5. MicroLAB
  6. 6. MicroLAB
  7. 7. What’s next <ul><li>Introduction </li></ul><ul><ul><li>MicroLAB </li></ul></ul><ul><ul><li>DRESD </li></ul></ul><ul><ul><ul><li>Philosophy </li></ul></ul></ul><ul><ul><ul><li>Team and meeting </li></ul></ul></ul><ul><ul><ul><li>Web </li></ul></ul></ul><ul><ul><ul><li>Results </li></ul></ul></ul><ul><ul><ul><li>In the world </li></ul></ul></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Basic principles </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><li>Reconfiguration @ PdM: DRESD </li></ul><ul><ul><li>Earendil flow </li></ul></ul><ul><ul><ul><li>DRESD-HLR </li></ul></ul></ul><ul><ul><ul><li>DRESD-BE </li></ul></ul></ul><ul><ul><li>DRESD Project examples </li></ul></ul><ul><li>Questions? </li></ul>
  8. 8. DRESD Philosophy <ul><li>Do or do not! There’s no try! </li></ul><ul><li>Master Yoda </li></ul><ul><li>I need to believe that something </li></ul><ul><li>extraordinary is possible! </li></ul><ul><li>Alicia Nash </li></ul>
  9. 9. DRESD Team @ September 2006 <ul><li>People </li></ul><ul><ul><li>32 Undergraduate students </li></ul></ul><ul><ul><li>12 Graduate students </li></ul></ul><ul><ul><li>3 PhD </li></ul></ul><ul><ul><li>1 Researchers </li></ul></ul><ul><ul><li>4 Professors </li></ul></ul><ul><li>Meeting </li></ul><ul><ul><li>Regular meeting every two weeks </li></ul></ul><ul><ul><li>DRESD Beer </li></ul></ul><ul><ul><li>3G-DRESD: the DRESD official meeting, August </li></ul></ul>
  10. 10. DRESD @ PdM <ul><li>and many more… </li></ul>
  11. 11. DRESD online <ul><li>http://www.dresd.org/ </li></ul><ul><li>http://www.dresd.org/forum/ </li></ul><ul><li>tel.elet.polimi.it/dwl </li></ul>
  12. 12. DRESD in regular curricula @ PdM a.a. 06/07 <ul><li>Undergraduate classes </li></ul><ul><ul><li>Logic Synthesis (projects) </li></ul></ul><ul><li>Graduate classes </li></ul><ul><ul><li>SW Laboratory (projects) </li></ul></ul><ul><ul><li>Computer Architecture (projects) </li></ul></ul><ul><ul><li>High Performance Processors and Systems (projects and regular class) </li></ul></ul><ul><ul><li>Soft Computing (projects) </li></ul></ul><ul><ul><li>IA and Robotics Lab (projects) </li></ul></ul><ul><ul><li>Hardware Design Methodologies (projects) </li></ul></ul><ul><ul><li>Hardware and Software Design Methodologies (projects) </li></ul></ul><ul><ul><li>Embedded Systems (projects) </li></ul></ul>
  13. 13. An example: RLA Project – How to <ul><li>Team </li></ul><ul><ul><li>Max team members: 3 </li></ul></ul><ul><ul><li>Team leader </li></ul></ul><ul><ul><ul><li>Create/maintain the project web-page </li></ul></ul></ul><ul><ul><ul><li>Upload the project documentation on the web-site </li></ul></ul></ul><ul><ul><ul><li>Prepare the project flayer </li></ul></ul></ul><ul><li>Project organization </li></ul><ul><ul><li>A first meeting to assign the project </li></ul></ul><ul><ul><li>A project proposal presentation (after 2-3 weeks max from the first meeting) </li></ul></ul><ul><ul><li>Project documentation and results </li></ul></ul><ul><ul><ul><li>A tex document presenting the project </li></ul></ul></ul><ul><ul><ul><li>A “ppt” final project presentation </li></ul></ul></ul><ul><ul><ul><li>The ZIP containing all the file of the project </li></ul></ul></ul><ul><ul><ul><li>A project demo: files and docs describing how to use the demo </li></ul></ul></ul><ul><li>MicroLAB logistic </li></ul><ul><ul><li>Access to the MicroLAB using the Politecnico ID Card </li></ul></ul><ul><ul><ul><li>Download the access module from the DRESD web site </li></ul></ul></ul><ul><ul><ul><li>Download the detail instruction document from the DRESD web site </li></ul></ul></ul><ul><ul><li>MicroLAB laptop connection </li></ul></ul><ul><ul><ul><li>Download the module form the DRESD web site </li></ul></ul></ul><ul><ul><ul><li>Fill the module with the required information </li></ul></ul></ul>
  14. 14. DRESD Results - Projects and Thesis <ul><li>The next 2 slides (11 - 12) present the number of students involved in MicroLAB activities for their undergraduate thesis work </li></ul><ul><ul><li>Slide 12 - a.a. 03/04 </li></ul></ul><ul><ul><li>Slide 14 – a.a. 04/05 </li></ul></ul><ul><ul><li>No distinction between DRESD and other MicroLAB activities has been done </li></ul></ul><ul><li>Slide 16 reports the number of student involved only in the DRESD project for their undergraduate thesis work </li></ul><ul><ul><li>From the a.a. 05/06 the number of students involved in DRESD allows to study and to monitor only this project </li></ul></ul><ul><li>Slide 18 lists the number of graduate degree originated by the DRESD project </li></ul>
  15. 15. “ Logic Synthesis” Class Project 03/04 Students working in the MicroLAB: 30
  16. 16. “ Logic Synthesis” Class Project 03/04 Students working in the MicroLAB: 30
  17. 17. “ Logic Synthesis” Class Project 04/05 Students working in the MicroLAB: 75
  18. 18. “ Logic Synthesis” Class Project 04/05 Students working in the MicroLAB: 75
  19. 19. “ Logic Synthesis” Class Project 05/06 Students working in the DRESD prj: 35
  20. 20. “ Logic Synthesis” Class Project 05/06 Students working in the DRESD prj: 35
  21. 21. Graduate Degree a.a 05/06 <ul><li>April ‘06: 1 </li></ul><ul><ul><li>SyCERS: a SystemC design exploration framework for the simulation of reconfigurable SoC architecture. </li></ul></ul><ul><li>July ‘06: 2 </li></ul><ul><ul><li>Task partitioning for the scheduling on partially dynamically reconfigurable FPGAs. </li></ul></ul><ul><ul><li>An hardware resources estimation framework for reconfigurable architecture. </li></ul></ul><ul><li>October ‘06: 1 </li></ul><ul><ul><li>A novel methodology for dynamically reconfigurable embedded systems design. </li></ul></ul><ul><li>December ‘06: 1 </li></ul><ul><ul><li>Task partitioning for the scheduling on reconfigurable systems driven by specification self-similarity. </li></ul></ul>
  22. 22. DRESD Results Conferences and Publications ’06 –’07 <ul><li>Published work: </li></ul><ul><ul><li>Papers: 15 </li></ul></ul><ul><ul><ul><li>Works presented (‘06): 10 </li></ul></ul></ul><ul><ul><ul><li>Works accepted (‘07): 5 </li></ul></ul></ul><ul><ul><li>Journal: 1 </li></ul></ul><ul><li>Guest editing: </li></ul><ul><ul><li>EURASIP Journal of Embedded Systems </li></ul></ul><ul><ul><li>Title: Reconfigurable computing and hardware/software codesign. </li></ul></ul><ul><li>Conferences Organization: </li></ul><ul><ul><li>Chair: 3 – ERSA06, ISCAS07, ERSA07 </li></ul></ul><ul><ul><li>PC: 5 – ERSA 06, 07; ReConfig 06, 07; RAW 07 </li></ul></ul><ul><ul><li>EC: 1 – ERSA 07 </li></ul></ul><ul><ul><li>Review </li></ul></ul><ul><ul><ul><li>International conferences </li></ul></ul></ul><ul><ul><ul><li>TVLSI </li></ul></ul></ul><ul><ul><ul><li>JSA </li></ul></ul></ul>
  23. 23. DRESD Results Partnerships/Collaborations @ August ‘06 <ul><li>Companies: </li></ul><ul><ul><li>Italian-European: </li></ul></ul><ul><ul><ul><li>Siemens Mobile, contact: Ferrara Giovanna </li></ul></ul></ul><ul><ul><ul><li>ATMEL, contacts: Ben Altieri, Piergiovanni Bazzana, Pier Stanislao, Chiara Nencioni </li></ul></ul></ul><ul><ul><li>American: </li></ul></ul><ul><ul><ul><li>Xilinx Inc., contacts: Jeff Weintraub, Monica Maccan </li></ul></ul></ul><ul><ul><ul><li>ImpulseC, contacts: David Buechner, David Pellerin </li></ul></ul></ul><ul><li>Italian Universities: </li></ul><ul><ul><li>Collegio Sant’Anna, Contact: prof. Marco Di Natale </li></ul></ul><ul><ul><li>Università degli studi di Milano, Contacts: prof. Vincenzo Piuri, prof. Roberto Cordone </li></ul></ul><ul><li>European Universities: </li></ul><ul><ul><li>ALaRI, contacts: prof.ssa Mariagiovanna Sami, prof. Umberto Bondi </li></ul></ul><ul><ul><li>Paderborn e Heinz Nixdoerf Institute, contact: prof. Mario Porman </li></ul></ul><ul><ul><li>Universitaet Karlsruhe, contact: prof. Juergen Becker </li></ul></ul><ul><ul><li>KTH - Royal Institute of Technology , contact: prof. Axel Jantsch </li></ul></ul><ul><li>Noth American Universities: </li></ul><ul><ul><li>UIC, contacts: prof. John Lillis, prof. Florin Balasa, prof. Shantanu Dutt, Lynn Thomas </li></ul></ul><ul><ul><li>Northwestern, contact: prof. Seda Ogrenci Memik </li></ul></ul><ul><ul><li>ITTC, contact: prof. David Andrews </li></ul></ul><ul><li>Asia: </li></ul><ul><ul><li>National Chung Cheng University - Taiwan, contact: prof. Pao-Ann Hsiung </li></ul></ul><ul><ul><li>University of Peradeniya – Sri Lanka, contact: prof. Sanath Alahakoon </li></ul></ul><ul><ul><li>King Mongkut's Institute of Technology - Thailand, contact: prof. Surin Kittitornkun </li></ul></ul><ul><ul><li>Computer Science and Engineering HCMC University of Technology – Vietnam, contact: prof. Dinh Duc Anh Vu </li></ul></ul><ul><ul><li>Walchand College of Engineering – India, contact: prof. Shaila Subbaraman </li></ul></ul>
  24. 24. DRESD in the WORLD @ August ‘06 <ul><li>Europe </li></ul><ul><ul><li>Paderborn University and HNI </li></ul></ul><ul><li>USA: </li></ul><ul><ul><li>UIC </li></ul></ul><ul><ul><li>Northwestern </li></ul></ul>
  25. 25. DRESD and HNI <ul><li>Partitioning and Scheduling </li></ul><ul><li>Static Scheduling for Reconfigurable Architecture </li></ul><ul><li>Placement and Scheduling </li></ul><ul><li>Linux on Raptor2000 </li></ul><ul><li>Dynamic Driver Generation for Custom IPs </li></ul><ul><li>Distributed reconfigurable scenarios </li></ul><ul><ul><li>Cluster Based and Network Based </li></ul></ul>
  26. 26. DRESD and UIC <ul><li>Memory management </li></ul><ul><ul><li>Deriving a multilevel memory architecture for distributed embedded systems optimized for area and/or reconfiguration, subject to performance constraints. </li></ul></ul><ul><ul><li>Definition of a novel set of metrics for self partial reconfigurable architecture, based memory information </li></ul></ul><ul><li>JHDL </li></ul><ul><ul><li>Extension JHDL to describe reconfigurable architecture </li></ul></ul><ul><ul><li>HW debugging using the JHDL framework </li></ul></ul><ul><li>UML </li></ul><ul><ul><li>Novel self reconfigurable </li></ul></ul><ul><ul><li>architecture description and </li></ul></ul><ul><ul><li>definition, based on UML </li></ul></ul>
  27. 27. <ul><li>It is common to consider HW components as fast but not flexible while SW solutions as flexible but slow. </li></ul><ul><li>With FPGA (in general, reconfigurable computing ): the HW domain has moved into the SW domain. </li></ul><ul><li>We aim to show also the SW domain might be moved closer into the HW. </li></ul><ul><ul><li>AC2SWA - Adaptive Computing to SW acceleration </li></ul></ul><ul><ul><li>AC4C - Adaptive Computing for Codesign </li></ul></ul>DRESD and Northwestern
  28. 28. What’s next <ul><li>Introduction </li></ul><ul><ul><li>MicroLAB </li></ul></ul><ul><ul><li>DRESD </li></ul></ul><ul><ul><ul><li>Philosophy </li></ul></ul></ul><ul><ul><ul><li>Team and meeting </li></ul></ul></ul><ul><ul><ul><li>Web </li></ul></ul></ul><ul><ul><ul><li>Results </li></ul></ul></ul><ul><ul><ul><li>In the world </li></ul></ul></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Basic principles </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><li>Reconfiguration @ PdM: DRESD </li></ul><ul><ul><li>Earendil flow </li></ul></ul><ul><ul><ul><li>DRESD-HLR </li></ul></ul></ul><ul><ul><ul><li>DRESD-BE </li></ul></ul></ul><ul><ul><li>DRESD Project examples </li></ul></ul><ul><li>Questions? </li></ul>
  29. 29. Reconfiguration <ul><li>The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation. </li></ul><ul><li>Gerald Estrin, 1960 </li></ul>
  30. 30. Reconfiguration in everyday life <ul><li>Soccer </li></ul>Hockey Football (Partial – Static) (Complete – Static) (Partial – Dynamic)
  31. 31. What’s next <ul><li>Introduction </li></ul><ul><ul><li>MicroLAB </li></ul></ul><ul><ul><li>DRESD </li></ul></ul><ul><ul><ul><li>Philosophy </li></ul></ul></ul><ul><ul><ul><li>Team and meeting </li></ul></ul></ul><ul><ul><ul><li>Web </li></ul></ul></ul><ul><ul><ul><li>Results </li></ul></ul></ul><ul><ul><ul><li>In the world </li></ul></ul></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Basic principles </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><li>Reconfiguration @ PdM: DRESD </li></ul><ul><ul><li>Earendil flow </li></ul></ul><ul><ul><ul><li>DRESD-HLR </li></ul></ul></ul><ul><ul><ul><li>DRESD-BE </li></ul></ul></ul><ul><ul><li>DRESD Project examples </li></ul></ul><ul><li>Questions? </li></ul>
  32. 32. Where we are working Partial Total
  33. 33. Where we are working Partial Embedded f i x
  34. 34. Where we are working Single Device Distributed System
  35. 35. What’s next <ul><li>Introduction </li></ul><ul><ul><li>MicroLAB </li></ul></ul><ul><ul><li>DRESD </li></ul></ul><ul><ul><ul><li>Philosophy </li></ul></ul></ul><ul><ul><ul><li>Team and meeting </li></ul></ul></ul><ul><ul><ul><li>Web </li></ul></ul></ul><ul><ul><ul><li>Results </li></ul></ul></ul><ul><ul><ul><li>In the world </li></ul></ul></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Basic principles </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><li>Reconfiguration @ PdM: DRESD </li></ul><ul><ul><li>Earendil flow </li></ul></ul><ul><ul><ul><li>DRESD-HLR </li></ul></ul></ul><ul><ul><ul><li>DRESD-BE </li></ul></ul></ul><ul><ul><li>DRESD Project examples </li></ul></ul><ul><li>Questions? </li></ul>
  36. 36. Earendil Design Flow: Basic Principles <ul><li>Modularity </li></ul><ul><ul><li>It is possible to use/design/manage a specific tool or the entire flow </li></ul></ul><ul><li>Scalability </li></ul><ul><ul><li>Easy to add or remove modules/projects </li></ul></ul><ul><li>Portability </li></ul><ul><ul><li>Earendil runs on different platforms: Linux, Mac OS X, Windows </li></ul></ul><ul><li>Ubiquity </li></ul><ul><ul><li>Decentralized collaboration to design and develop the Earendil project </li></ul></ul>
  37. 37. Earendil Design Flow: an Overview DRESD - HLR DRESD - BE
  38. 38. DRESD - HLR
  39. 39. DRESD - BE
  40. 40. What’s next <ul><li>Introduction </li></ul><ul><ul><li>MicroLAB </li></ul></ul><ul><ul><li>DRESD </li></ul></ul><ul><ul><ul><li>Philosophy </li></ul></ul></ul><ul><ul><ul><li>Team and meeting </li></ul></ul></ul><ul><ul><ul><li>Web </li></ul></ul></ul><ul><ul><ul><li>Results </li></ul></ul></ul><ul><ul><ul><li>In the world </li></ul></ul></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Basic principles </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><li>Reconfiguration @ PdM: DRESD </li></ul><ul><ul><li>Earendil flow </li></ul></ul><ul><ul><ul><li>DRESD-HLR </li></ul></ul></ul><ul><ul><ul><li>DRESD-BE </li></ul></ul></ul><ul><ul><li>DRESD Project examples </li></ul></ul><ul><li>Questions? </li></ul>
  41. 41. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  42. 42. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  43. 43. Reconfigurable Hardware: why?
  44. 44. Reconfigurable Hardware: why?
  45. 45. Motivations <ul><li>Increasing need for behavioral flexibility in embedded systems design </li></ul><ul><ul><li>Support of new standards, e.g. in media processing </li></ul></ul><ul><ul><li>Addition of new features </li></ul></ul><ul><li>Applications too large to fit on the device all at once </li></ul><ul><li>Current configurable devices allow us to obtain this </li></ul><ul><ul><li>FPGAs </li></ul></ul><ul><li>However, we need a way to process a specification to make it suitable for reconfigurable implementation </li></ul>
  46. 46. Aims <ul><li>Define and implement a partitioning approach to produce descriptions of module-based reconfigurable systems from a specification </li></ul><ul><li>In particular: </li></ul><ul><ul><li>Propose an algorithm to produce partitioning candidates </li></ul></ul><ul><ul><li>Propose criteria to evaluate the candidates </li></ul></ul><ul><ul><li>Use a proven scheduling and allocation approach for reconfigurable systems to complete the flow </li></ul></ul>
  47. 47. Core Generation <ul><li>Process the specification graph, producing a set of clusters possibly to be used as configurable modules </li></ul><ul><li>Self-similarity: rationale </li></ul><ul><ul><li>Configuring modules onto an FPGA takes time </li></ul></ul><ul><ul><li>Identifying recurrent structures allows us to reuse them </li></ul></ul><ul><ul><li>Gain in reconfiguration time, thus better performance </li></ul></ul><ul><li>Extracting regularity means detecting isomorphism </li></ul>
  48. 48. Core Generation <ul><li>Result of the core generation phase: </li></ul><ul><li>Choice of which of the identified cores to use </li></ul><ul><ul><li>Policies: LFF, MFF… </li></ul></ul><ul><li>Greedy approach: choose the winning core, then eliminate the overlapping ones </li></ul>
  49. 49. Cover Generation
  50. 50. Cover Generation
  51. 51. Cover Generation: Result
  52. 52. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  53. 53. YaRA: the embedded 1D approach
  54. 54. YaRA: fixed side
  55. 55. YaRA: FPGA Layers Clock Modulo Riconf. Macro HW PPC-405 BRAM e Moltiplicatori 18x18 Parte Fissa CLB x CLB y Layer
  56. 56. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  57. 57. The Acheronte flow
  58. 58. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  59. 59. How to extend YaRA and Acheronte <ul><li>The “YaRA” side: </li></ul><ul><ul><li>HW-IPCM </li></ul></ul><ul><ul><li>D-ICAP </li></ul></ul><ul><ul><li>BiRF </li></ul></ul><ul><ul><li>IP-Core Generator Tool </li></ul></ul><ul><ul><li>EDK System Creator </li></ul></ul><ul><li>The “Acheronte” side: </li></ul><ul><ul><li>BUBA </li></ul></ul><ul><ul><li>ComIC </li></ul></ul><ul><ul><li>ADG </li></ul></ul><ul><ul><li>BAnMaT </li></ul></ul>
  60. 60. D-ICAP: DRESD - ICAP <ul><li>Objectives </li></ul><ul><ul><li>Define the DRESD – ICAP core, characterized by the following parameters: </li></ul></ul><ul><ul><ul><li>Support for different bus infrastructure </li></ul></ul></ul><ul><ul><ul><li>Custom buffer memory dimension </li></ul></ul></ul><ul><ul><ul><li>Support DMA communication </li></ul></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Create a tool able to design a specific D-ICAP IP-Core according to the listed parameters </li></ul></ul>
  61. 61. BiRF: Bitstream Relocation Filter <ul><li>Objectives </li></ul><ul><ul><li>Automatic replacement of a reconfiguration bitstream </li></ul></ul><ul><ul><li>HW implementation of such a filter to speed-up its execution </li></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Target: reduce the amount of memory used to store partial bitstreams in dynamically self reconfiguring systems based on column-wise approach </li></ul></ul><ul><ul><li>Methodology: bitstream relocation </li></ul></ul><ul><ul><li>Solution: an hardware filter created to perform internal bitstream relocation </li></ul></ul>
  62. 62. <ul><li>Objectives </li></ul><ul><ul><li>Realize a framework able to automatically generate an IP-Core starting from an already existing core, provided by the user. </li></ul></ul><ul><ul><li>Support the PLB, OPB and the Wishbone BUS infrastructure </li></ul></ul><ul><ul><li>Fully support the YARA architecture </li></ul></ul><ul><ul><li>EDK compatible </li></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Reduce the overall IP-Core design time; </li></ul></ul><ul><ul><li>Speedup the reconfigurable cores generation phase in the Acheronte workflow; </li></ul></ul><ul><ul><li>Increment cores reuse with different communication infrastructures. </li></ul></ul>IP-Core Generator Tool
  63. 63. EDK System Creator <ul><li>Objectives </li></ul><ul><ul><li>Given a known EDK system architecture and a generic IP-Core description </li></ul></ul><ul><ul><ul><li>Automatic binding of the two inputs into a downloadable and executable bitstream </li></ul></ul></ul><ul><ul><li>Fully support the YARA architecture </li></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Speedup the creation of the YaRA fixed side according to the specific IP-core belonging to the input specification </li></ul></ul><ul><ul><li>Full-automatic support to the YaRA fixed side generation phase, combining it with the IPGen tool </li></ul></ul>
  64. 64. BUBA <ul><li>Objectives </li></ul><ul><ul><li>Assign the placement constraints for a reconfigurable core to be used with the YARA architecture </li></ul></ul><ul><ul><li>Find the best floorplanning constraints according with different optimization function, e.g. #AssignedCLBs/#UsedCLBs </li></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Automatic generation of the correct placement constraints into the UCF file for a self reconfigurable architecture </li></ul></ul>
  65. 65. ComIC <ul><li>Objectives </li></ul><ul><ul><li>Create the communication infrastructure for a given instance of the YARA architecture </li></ul></ul><ul><ul><li>Automatic XDL description manipulation to define the correct MacroHW for the bus infrastructure </li></ul></ul><ul><li>Rationale </li></ul><ul><ul><li>Provide a full-automatic support to the generation phase of the communication infrastructure </li></ul></ul>
  66. 66. ADG: Automatic Driver Generator <ul><li>Objectives </li></ul><ul><ul><li>Complete the IP-Core Generator tool work with the creation of the correct driver for a given IP-Core </li></ul></ul><ul><ul><li>Create the basic infrastructure for both the standalone and the OS version of the driver </li></ul></ul>
  67. 67. BAnMaT: Bitstream Analizer Manipulator Tool <ul><li>Objectives </li></ul><ul><ul><li>Bitstream analyzer </li></ul></ul><ul><ul><li>Easy API to manage the bitstream file </li></ul></ul><ul><ul><li>Difference bitstream file checker </li></ul></ul><ul><ul><li>Reconfiguration bitstream debugger </li></ul></ul>
  68. 68. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  69. 69. Linux and reconfiguration software architecture
  70. 70. Socket communication
  71. 71. Devices communication
  72. 72. Architectural Layers
  73. 73. R econfiguration O f T he F PGA with L inux <ul><li>Reconfiguration Manager </li></ul><ul><ul><li>Module Manager </li></ul></ul><ul><ul><li>Allocation Manager </li></ul></ul><ul><ul><li>Positioning Manager </li></ul></ul>
  74. 74. L oad O n L inux <ul><li>Device Driver Manager </li></ul><ul><ul><li>Kernel module loading </li></ul></ul><ul><ul><li>Kernel module unloading </li></ul></ul><ul><li>Device Manager </li></ul><ul><ul><li>Add device (/dev/…) </li></ul></ul><ul><ul><li>Remove device </li></ul></ul>
  75. 75. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  76. 76. Microlinux
  77. 77. Microlinux structure Kernel Source RamDisk image zImage.elf zImage.initrd.elf U-Boot & Bitstream Deployment on the board
  78. 78. Microlinux on Xilinx Virtex II Pro Virtex II Pro S D R A M F L A S H Driver Kernel APs MicroLinux boot image copy load boot contiene Absolute physical addresses
  79. 79. Development framework and compilation chain Xilinx Platform Studio Xparameters.h ./genMicroLinux Kernel Image <ul><li>Modular </li></ul><ul><li>Scalable </li></ul><ul><li>Small </li></ul>eMdev :
  80. 80. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  81. 81. SyCERS - Objectives <ul><li>Define a novel model to describe reconfigurable systems </li></ul><ul><ul><li>Based on know HDL (no new languages) </li></ul></ul><ul><ul><li>To be used in the early first stage of the project; to consider the reconfiguration at the system level </li></ul></ul><ul><li>Propose a complete framework for the simulation and the design of reconfigurable systems </li></ul><ul><ul><li>Providing system specification that can be simulated </li></ul></ul><ul><ul><li>Allowing fast parameters setting, e.g. number of reconfigurable blocks, reconfigurable time </li></ul></ul><ul><ul><li>Taking into account the software side of the final system </li></ul></ul>
  82. 82. TLM e SystemC <ul><li>In TLM the system is first described at an high level of abstraction where communication details are hidden </li></ul><ul><li>The key concept of TLM is the separation of functionality definitions from communication details </li></ul><ul><ul><li>to achieve this TLM uses through the concept of channel </li></ul></ul><ul><ul><ul><li>DEF.: SystemC channel is a class that implements one or more SystemC interface classes. A channel implements all the methods of the inherited interface classes. </li></ul></ul></ul><ul><ul><ul><li>DEF.: A SystemC port is a class template with and inheriting from a SystemC interface. Ports allow access of channels across module boundaries. </li></ul></ul></ul><ul><ul><ul><li>DEF.: A SystemC interface is an abstract class that provides only pure virtual declarations of methods referenced by SystemC channels and ports. </li></ul></ul></ul><ul><li>SystemC, starting from the 2.0 version, support TLM using the following structures: </li></ul>write() read() module A pA->write(v) module B v=pB->read() channel pA pB sc_interface sc_port
  83. 83. The SyCERS methodology Specification Model Component Assembly Model Bus Functional Model <ul><li>Define the system functionality </li></ul><ul><ul><li>No information regarding the final implementation </li></ul></ul><ul><li>Solution space exploration </li></ul><ul><ul><li>Provides the functionalities implementation details </li></ul></ul><ul><ul><li>No information regarding the communication </li></ul></ul><ul><li>Computed solution validation via the simulation </li></ul>
  84. 84. A reconfigurable component using SystemC <ul><li>It’s not possible to instantiate an sc_module during the simulation phase </li></ul><ul><li>It’s possible to modify the SC_THREAD and the SC_METHOD via: </li></ul><ul><ul><li>function pointer </li></ul></ul><ul><ul><li>sc_mutex </li></ul></ul><ul><li>Configuration </li></ul><ul><ul><ul><li>Combined with the reconfiguration time </li></ul></ul></ul><ul><li>Elaboration </li></ul><ul><ul><ul><li>Provided with the elaboration time </li></ul></ul></ul>*g() Reconfigurable Component (sc_module) Configuration (function pointer) mutex
  85. 85. Reconfigurable component behavior
  86. 86. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  87. 87. LimboWARE: The idea <ul><li>The basic idea is to postpone the decision of whether executing a task in HW or in SW moving it at run-time </li></ul><ul><li>This will be done not for every task, because of code memory overhead, but only where is not possible to take a wise choice at design or compile-time </li></ul>
  88. 88. LimboWARE: When - Where <ul><li>Compile-time Unbounded number of execution </li></ul><ul><ul><li>If n is a number known only at run-time. The limbo choice is wiser than the corresponding one done at compile time (without this information) </li></ul></ul><ul><ul><li>for(i=0; i<n; i++){ </li></ul></ul><ul><ul><li> function(); </li></ul></ul><ul><ul><li>} </li></ul></ul><ul><li>Execution trace dependent choice between HW and µ-code </li></ul><ul><ul><li>Functionality already in HW (past) </li></ul></ul><ul><ul><li>Functionality that in this branch will be used many times (constrained future) </li></ul></ul>
  89. 89. LimboWARE: Execution path dependent choice <ul><li>The execution of node 6 depends on the path </li></ul><ul><ul><li>If the path is 1-3-5-6 the predicate P is TRUE, is executed in HW and the relative µ-code for the SW execution is skipped, by branching after </li></ul></ul><ul><ul><li>If the path is 2-4-5-6, the predicate P is FALSE, HW_CALL and JMP are not executed and the µ-code for is executed </li></ul></ul>
  90. 90. DRESD Project examples <ul><li>HLR </li></ul><ul><ul><li>Some theoretical aspects </li></ul></ul><ul><li>YaRA </li></ul><ul><ul><li>The reconfigurable architecture </li></ul></ul><ul><li>Acheronte </li></ul><ul><ul><li>The back-end design flow </li></ul></ul><ul><li>YaRA and Acheronte extension </li></ul><ul><li>LINUX </li></ul><ul><ul><li>Reconfiguration operating System support </li></ul></ul><ul><ul><li>Microlinux </li></ul></ul><ul><li>SyCERS </li></ul><ul><ul><li>The simulation framework </li></ul></ul><ul><li>LimboWARE </li></ul><ul><ul><li>Reconfigurable computing, some new idea </li></ul></ul><ul><li>VIRGIL </li></ul><ul><ul><li>A new possible flow </li></ul></ul>
  91. 91. VIRGIL: Workflow HLR
  92. 92. VIRGIL: The Compiler
  93. 93. What’s next <ul><li>Introduction </li></ul><ul><ul><li>MicroLAB </li></ul></ul><ul><ul><li>DRESD </li></ul></ul><ul><ul><ul><li>Philosophy </li></ul></ul></ul><ul><ul><ul><li>Team and meeting </li></ul></ul></ul><ul><ul><ul><li>Web </li></ul></ul></ul><ul><ul><ul><li>Results </li></ul></ul></ul><ul><ul><ul><li>In the world </li></ul></ul></ul><ul><li>Reconfiguration </li></ul><ul><ul><li>Basic principles </li></ul></ul><ul><ul><li>Where we are working </li></ul></ul><ul><li>Reconfiguration @ PdM: DRESD </li></ul><ul><ul><li>Earendil flow </li></ul></ul><ul><ul><ul><li>DRESD-HLR </li></ul></ul></ul><ul><ul><ul><li>DRESD-BE </li></ul></ul></ul><ul><ul><li>DRESD Project examples </li></ul></ul><ul><li>Questions? </li></ul>
  94. 94. Questions

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