Design of a BPSK and QPSK digital Modulation scheme and its implementation on FPGAs for universal mobile telecommunications system and SDR applications. The simulation of the system is made in MATLAB Simulink environment and System Generator, a tool used for FPGA design. Hardware Co-Simulation is designed using VHDL a hardware description language targeting a Xilinx FPGA and is verified using MATLAB Simulink. It is then converted to VHDL level using Simulink HDL coder. The design is synthesized and fitted with Xilinx 14.2 ISE Edition software, and downloaded to Spartan 3E (XC3S500E) board.