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Memory types and logic families
1. UNIT IV
Memory Types & Logic Families
By Dr. Dhobale J V
Associate Professor
School of Engineering & Technology
RNB Global University, Bikaner
RNB Global University, Bikaner. 1Course Code - 19004000
2. Objectives
Static and Dynamic, Representative circuits for
cells using BJT and FETs
Timing diagrams of memories.
Memory expansion using Ics.
Flash memory, CCD, latest trends in
memories.
Logic circuits.
2RNB Global University, Bikaner.Course Code - 19004000
3. Memories
A memory is neither a sequential circuit (since
we require sequential circuits to be clocked,
and memories are not clocked), nor
a combinatorial circuit, since its output values
depend on past values.
In general, a memory has m inputs that are
called the address inputs that are used to
select exactly one out of 2m
words, each one
consisting of n bits.
3RNB Global University, Bikaner.Course Code - 19004000
4. Memories
It has n connectors that are bidirectional that
are called the data lines.
These data lines are used both as inputs in
order to store information in a word selected
by the address inputs, and as outputs in order
to recall a previously stored value.
Such a solution reduces the number of
required connectors by a factor two.
Finally, it has an input called enable that
controls whether the data lines have defined
states or not, and an input called r/w that
determines the direction of the data lines. 4RNB Global University, Bikaner.Course Code - 19004000
5. Memories
A memory with an arbitrary value of m and an
arbitrary value of n can be built from memories
with smaller values of these parameters.
To show how this can be done, we first show
how a one-bit memory (one with m = 0 and n =
1) can be built. Here is the circuit:
5RNB Global University, Bikaner.Course Code - 19004000
7. Memories
The central part of the circuit is an SR-latch
that holds one bit of information.
When enable is 0, the output d0 is isolated both
from the inputs to and the output from the SR-
latch.
Information is passed from d0 to the inputs of
the latch when enable is 1 and r/w is 1
(indicating write).
Information is passed from the
output x to d0 when enable is 1 and r/w is 0 (i
ndicating read). 7RNB Global University, Bikaner.Course Code - 19004000
8. Memories
Now that we know how to make a one-bit
memory, we must figure out how to make
larger memories.
First, suppose we have n memories of
2m
words, each one consisting of a single bit.
We can easily convert these to a single
memory with 2m
words, each one consisting of
a n bits. Here is how we do it:
8RNB Global University, Bikaner.Course Code - 19004000
10. Memories
Memory structures are critical to any large,
complex digital design.
Memory structures are crucial in digital design.
– ROM, PROM, EPROM, RAM, SRAM,
(S)DRAM, RDRAM.
All memory structures have an address bus
and a data bus
– Possibly other control signals to control
output etc.
10RNB Global University, Bikaner.Course Code - 19004000
11. Memories
E.g. 4 Bit Address bus with 5 Bit Data Bus.
11RNB Global University, Bikaner.Course Code - 19004000
12. Memories
Internal organisation -
– ‘Lookup Table of values’
– For each address there is a corresponding
data output.
12RNB Global University, Bikaner.Course Code - 19004000
13. Memories
Usually consider a repository for data or
program code.
Indexing of the data and ability to both read
and write suggests a mailslot analogy.
– Byte = 8 bits
– Word = whatever data width you’re using
But, especially when considering ‘read only’,
‘Lookup Table’ ≡ ‘Truth Table”.
13RNB Global University, Bikaner.Course Code - 19004000
15. Memories
Data memory types:
1. Random Access Memory which can be read &
written
Static & Dynamic RAM
2. Read Only Memory which retains data
PROM, EPROM, EEPROM, Flash
15RNB Global University, Bikaner.Course Code - 19004000
17. Memories
Static RAM (SRAM)
Random Access Memory
Static: Data value is retained as long as VDD
is present.
Random Access: Any location can read at a
point in time.(Doesn’t need sequential
addresses).
17RNB Global University, Bikaner.Course Code - 19004000
18. Memories
Static RAM (SRAM):
SRAM can be built using either:
D-type latch
6-transistor CMOS RAM cell
D-type Latch
Used for building CPU registers, etc
Derived from inverted S-R flipflop
18RNB Global University, Bikaner.Course Code - 19004000
21. Memories
Static RAM (SRAM):
When the Enable line is zero (En=0)
/S = /R = 1 and the inverting SR flipflop retains its
previous value.
When the enable line is high (En=1)
The value of data line D is latched into the flipflop.
21RNB Global University, Bikaner.Course Code - 19004000
22. Memories
Static RAM (SRAM):
When the Enable line is zero (En=0)
/S = /R = 1 and the inverting SR flipflop retains its
previous value.
When the enable line is high (En=1)
The value of data line D is latched into the flipflop.
Each BIT would need 16 transistors (NAND
gate = 4 transistors)
For large SRAM modules not very efficient.
o 1-MB SRAM -> 8-Mb -> 128 Million transistors
22RNB Global University, Bikaner.Course Code - 19004000
23. Memories
ROM: Most basic type of ROM is factory-
programmed diode matrix.
23RNB Global University, Bikaner.Course Code - 19004000
24. Memories
ROM:
The diode can be replaced by a multiple emitter
transistor for each data word.
During manufacture, a diode is placed at those
connections which are required by the customer.
Complete transistor array is programmed via
fabrication mask
Those connections without diode cannot be changed
later and vice-versa
Memory is read-only
ROM is economic when several thousand devices are
needed.
24RNB Global University, Bikaner.Course Code - 19004000
25. Memories
PROM:
ROM device is factory-programmed device
Need to tell fab plant which connections to make/skip
More useful solution would be to allow customer to
program device in the field.
Place diode at every junction with nichrome fusible link
in series.
Any link can be blown by selecting its address and
applying a high voltage to its data output
Once fuse has been blown it cannot be repaired.
Memory is read-only.
25RNB Global University, Bikaner.Course Code - 19004000
26. Memories
PROM:
Advantage over ROM
Device is ‘field-programmable’:
Customer can buy a blank PROM to programme
Manufacturer can made identical PROM for every
customer, reducing cost
Disadvantages over ROM
Need 2 voltages:
Operating voltage
Programming voltage
26RNB Global University, Bikaner.Course Code - 19004000
28. Memories
Memory Timing Diagram:
RAS : Row Address Strobe, a terminology
holdover from asynchronous DRAM.
CAS : Column Address Strobe, a terminology
holdover from asynchronous DRAM.
TWR : Write Recovery Time, the time that must
elapse between the last write command to a
row and precharging it. Generally, TRAS = TRCD +
TWR.
TRC : Row Cycle Time. TRC = TRAS + TRP.
28RNB Global University, Bikaner.Course Code - 19004000
30. Memories
Flash Memory:
Flash memory is a non-volatile memory chip
used for storage and for transfering data
between a personal computer (PC) and digital
devices.
It has the ability to be
electronically reprogrammed and erased. It is
often found in USB flash drives, MP3 players,
digital cameras and solid-state drives.
30RNB Global University, Bikaner.Course Code - 19004000
31. Memories
Flash Memory:
Flash memory is a type of
nonvolatile memory that erases data in units
called blocks.
A block stored on a flash memory chip must
be erased before data can be written, or
programmed, to the microchip. Flash
memory retains data for an extended period of
time whether a flash-equipped device is
powered on or off.
31RNB Global University, Bikaner.Course Code - 19004000
33. Logic Families - History
The first transistors were fabricated in 1947 at
Bell Laboratories (Bell Labs) by Brattain with
Bardeen providing the theoretical background
and Shockley managed the activity.
– The trio received a Nobel Prize in Physics
for their work in 1956.
The transistor was called a point-contact
transistor and was a type of bipolar junction
transistor (BJT).
33RNB Global University, Bikaner.Course Code - 19004000
34. Logic Families - History
The theory on field effect transistors (FETs)
was developed much earlier than our
understanding of BJTs .
– First patent on FETs dates from 1925
• Julius Edgar Lilienfeld, an Austro-Hungarian
physicist.
However, the quality of the semiconductor and
the oxide materials were barriers to developing
good working devices.
– The first FET was not invented until 1959
• Dawon Kahng and Martin M. (John) Atalla of Bell Labs
34RNB Global University, Bikaner.Course Code - 19004000
35. Logic Families - History
Integrated circuits (ICs) are chips, pieces of
semiconductor material, that contain all of the
transistors, resistors, and capacitors
necessary to create a digital circuit or system.
The first ICs were fabricated using Ge BJTs in
1958.
Jack Kirby of Texas Instruments, Nobel Prize in
2000
Robert Noyes of Fairchild Semiconductors
fabricated the first Si ICs in 1959.
35RNB Global University, Bikaner.Course Code - 19004000
36. Logic Families - History
Integration Level:
SSI Small scale integration - 12 gates/chip
MSI Medium scale integration - 100 gates/chip
LSI Large scale integration - 1K gates/chip
VLSI Very large scale integration - 10K gates/chip
ULSI Ultra large scale integration - 100K gates/chip.
36RNB Global University, Bikaner.Course Code - 19004000
37. Logic Families - History
Moore’s law:
A prediction made by Moore (a co-founder of
Intel) in 1965: “… a number of transistors to
double every 2 years”.
37RNB Global University, Bikaner.Course Code - 19004000
38. Logic Families
Logic families are sets of chips that may
implement different logical functions, but use
the same type of transistors and voltage levels
for logical levels and for the power supplies.
These families vary by speed, power
consumption, cost, voltage & current levels.
38RNB Global University, Bikaner.Course Code - 19004000
40. Logic Families
Digital IC Terminology: Voltage Parameters
VIH(min): high-level input voltage, the minimum
voltage level required for a logic 1 at an input.
VIL(max): low-level input voltage
VOH(min): high-level output voltage
VOL(max): low-level output voltage
40RNB Global University, Bikaner.Course Code - 19004000
41. Logic Families
Digital IC Terminology: Voltage Parameters
For proper operation the input voltage levels to a logic
must be kept outside the indeterminate range.
Lower than VIL(max) and higher than VIH(min).
41RNB Global University, Bikaner.Course Code - 19004000
42. Logic Families
Digital IC Terminology: Noise Margin
Noise is present in all real systems.
This adds random fluctuations to voltages
representing logic levels.
To cope with noise, the voltage ranges defining the
logic levels are more tightly constrained at the output
of a gate than at the input.
Thus small amounts of noise will not affect the circuit.
The maximum noise voltage that can be tolerated by a
circuit is termed its noise immunity (noise Margin).
42RNB Global University, Bikaner.Course Code - 19004000
43. Logic Families
Digital IC Terminology: fanout –
The maximum number of standard logic inputs
that an output can drive reliably.
Also known as the loading factor.
43RNB Global University, Bikaner.Course Code - 19004000
44. Logic Families
Digital IC Terminology: Power Requirements –
Every IC needs a certain amount of electrical
power to operate.
Vcc (TTL)
VDD(MOS)
44RNB Global University, Bikaner.Course Code - 19004000
45. Logic Families
Digital IC Terminology: Speed-Power Product
Desirable properties:
Short propagation delays (high speed).
Low power dissipation
Speed-power product measures the combined
effect.
45RNB Global University, Bikaner.Course Code - 19004000
47. Logic Families
Interfacing logic families: Voltage
In some interfacing situations, a HIGH output
pin may produce a voltage that is too low to be
recognized as a HIGH by the input pin it’s
connected to.
The solution in such cases is to use a pull-up
resistor.
47RNB Global University, Bikaner.Course Code - 19004000
48. Logic Families
Interfacing logic families: Voltage
Example: TTL to CMOS
A TTL HIGH output may be as low as 2.4 V.
But a CMOS input expects HIGHs to be at least 3.33 V
48RNB Global University, Bikaner.Course Code - 19004000
49. Logic Families
Interfacing logic families: Current
In some interfacing situations, either a HIGH
output pin may not source enough current to
drive the input pin it’s connected to, or a LOW
output pin may not sink enough current to
drive the input pin it’s connected to.
The solution in such cases is to use a buffer.
49RNB Global University, Bikaner.Course Code - 19004000
50. Logic Families
Interfacing logic families: Current
Example: CMOS to TTL
A CMOS LOW output can only sink 0.51 mA.
But as much as 1.6 mA may flow out of a TTL LOW
input.
It can also be used for increasing the fanout.
50RNB Global University, Bikaner.Course Code - 19004000
51. Logic Families
Diode Logic (DL) –
Simplest; does not scale.
NOT not possible (need an active element).
51RNB Global University, Bikaner.Course Code - 19004000
52. Logic Families
Resistor-Transistor Logic (RTL) –
Replace diode switch with a transistor switch.
Can be cascaded.
Large power draw.
52RNB Global University, Bikaner.Course Code - 19004000
53. Logic Families
Diode-Transistor Logic (DTL)-
Essentially diode logic with transistor
amplification.
Reduced power consumption.
Faster than RTL.
53RNB Global University, Bikaner.Course Code - 19004000
54. Logic Families
TTL: Transistor-Transistor Logic:
First introduced by in 1964 (Texas Instruments).
TTL has shaped digital technology in many ways.
One of the most widely used families for small- and
medium-scale devices.
Rarely used for VLSI.
Standard TTL family (e.g. 7400) is obsolete.
High switching speed (125 MHz).
Less noise.
More current (3 mA) driving capability.
54RNB Global University, Bikaner.Course Code - 19004000
56. Logic Families
TTL: Family Evolution:
56RNB Global University, Bikaner.Course Code - 19004000
57. Logic Families
ECL- Emitter-Coupled Logic:
Based on BJT, but removes problems of delay time by
preventing the transistors from saturating.
Very fast operation - propagation delays of 1ns or less.
High power consumption, perhaps 60 mW/gate.
Logic levels. “0”: –1.7V. “1”: –0.8V.
Such strange logic levels require extra effort when
interfacing to TTL/CMOS logic families.
Low noise immunity of about 0.2-0.25 V.
Used in some high speed specialist applications, but
now largely replaced by high speed CMOS.
57RNB Global University, Bikaner.Course Code - 19004000
58. Logic Families
CMOS - Complimentary Metal-oxide
semiconductor :
Considerably lower energy consumption than TTL and
ECL, which has made portable electronics possible.
Most widely used family for large-scale devices.
Combines high speed with low power consumption.
Usually operates from a single supply of 5 – 15 V.
Excellent noise immunity of about 30% of supply
voltage.
Can be connected to a large number of gates (about
50).
58RNB Global University, Bikaner.Course Code - 19004000
59. Logic Families
CMOS - Complimentary Metal-oxide
semiconductor : Family Evolution:
59RNB Global University, Bikaner.Course Code - 19004000
60. Reviews
Static and Dynamic, Representative circuits for
cells using BJT and FETs
Timing diagrams of memories.
Memory expansion using Ics.
Flash memory, CCD, latest trends in
memories.
Logic circuits.
60RNB Global University, Bikaner.Course Code - 19004000