Semiconductor memories; RAM, SRAM,DRAM,ROM,PROM,EPROM,EEPROM.

1. Dr. Ram Manohar Lohiya
Awadh University Ayodhya.
(Seminar SESSION 2020)
Presentation_Based on MOOC
Completed through Swayam &
Offered by NPTEL .

2. MEMORY ”Digital electronic circuits”
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By-
Shakti Pratap
M.Sc. Electronics (2nd Sem.)
(Department of Physics & Electronics)
Dr. RML AVADH UNIVERSITY, AYODHYA
Contact me!

3. Objectives:
● Begin with memory: An intro.
● List the various forms of memory.
● Discuss memory addressing
techniques.
● The basic features of SRAM and
DRAM chips.
● Describe ROM, PROM, and EPROM
and their characteristics.

4. An Intro. of Memory-
“Circuits and/or systems designed specifically for data
storage are referred to as memory.”
In the simplest application, the memory may be a flip-flop, or perhaps
a number of flip-flops connected to form a register.
Memory/Storage Categories:
Category_1
● Main Memory
● Primary Memory
● Internal Memory
Category_2
● Secondary Memory/Storage
● Auxiliary memory/Storage
● External Memory/Storage

5. Characteristics:
● Volatility
1. Volatile
2. Non-volatile
● Mutability
1. Read/Write
2. Read Only
● Accessibility
1. Random Access
2. Direct Access
3. Sequential Access
Measuring Units;
● BIT: Binary digit(1or0)
● NIBBLE: 4BITS
● Byte: 8bits
● Word: 16bits/2Bytes
● DWORD: 32BITS/4BYTES
● QWORD: 64BITS/8BYTES

6. Various forms of memory(PRIMARY MEMORIES)
RAM (Random Access Memory) is volatile, meant for multiple read and
write (Read/Write Memory).
ROM (Read Only Memory) is non-volatile, meant for multiple reading, also
random access.
If m address lines,memory size - (2^m) x n.

7. I/O Methods:
Separate I/O:
Control logic
CS R WR RD
0 0 1 0
0 1 0 1
1 0 0 0
1 1 0 0
Tri-state Buffer
Amplifier

8. COMMON I/O METHOD
Common I/O lines save number of external pins.
MEMORY IC ORGANIZATION No OF PINS TYPE
2114 1K X 4 18 COMMON
2115 1K X 1 16 SEPARATE

9. MEMORY CELL ADDRESSING
Linear Addressing
IC 7489, 16 x 4, 64 bit RAM follows this
(word addressing)

10. Matrix Addressing
● Square array requires fewest lines to address a cell / group of cells (word-
organized) in particular location.
● No. of address bits coming to address decoder(s) of memory IC remains same.

11. MEMORY READ CYCLE
Read cycle time (t read-cycle ):Time to be allowed between two
consecutive valid addresses for memory read.
Access time (t access ): Time to be allowed between placement of
stable address and availability of stable data.
Hold time (t hold ): Amount
of time output data is to
remain valid after the
address is changed.
t cs-access and t cs-
hold are similar
quantities but w.r.t.
CS signal.

12. MEMORY WRITE CYCLE
Write cycle time (t write-cycle ): Time to be allowed between two consecutive
valid addresses for memory write (≈100 ns).
Setup time (t setup ): Minimum time between placement of valid address and
write enable.
Data write time overlap (t overlap ): Minimum time input to remain stable before
write disables.
Data hold time (t data-hold ):
Minimum time data to remain
valid after write disables.
Similarly, t address-hold.
Write enable time (t write-
enable ):
Minimum time required for
write to remain enabled.

13. SRAM
SRAM (Static RAM: BJT, MOS)
in contrast to DRAM (Dynamic
RAM: MOS) does not require
refreshing.
● Control Logic: It decides when
the chip is selected whether D
in is to be written in the cell or
the cell is to be read out
through D out .
● Write Amplifier: It contains
circuitry to send current to
memory cell as per D in to
effect switching when
required.
● Read Amplifier: It contains
circuitry to sense the current
from a cell and delivers
appropriate output D out .

14. BJT MEMORY CELL
Reading from the Cell
Many such cells in parallel connect to Data
lines with common Read / Write circuit.
Individual cell is addressed by row select (X)
and column select (Y) lines.
Logic LOW is ≤ 0.3V and logic HIGH is ≥
3.0V.
A bias voltage of 0.5V is applied to emitters
ED 0 and ED 1
● Memory cell is addressed by making X = Y = H.
➔ Consider, Q 0 is ON and Q 1 is OFF is
storage of 1 in the cell.
Current flows from ED 0 via Data
through base Q 2 making Q 2 ON.
D out is L.
No current flows from ED 1 via
Data through base Q 3 and thus, Q 3
is OFF. D out is H.
➔ Similarly, for Q 0 OFF and Q 1 ON, D
out is L and D out is H.

15. Writing into the Cell
If CS’=H,(NO OPERATIONS)
If CS’=L,R/W’=H,X&Y=H,( READ OPERATION)
If CS’=L,R/W’=L,X&Y=H,(WRITE OPERATION)

16. DRAM(DYNAMIC RAM)
DRAM Basics and Multiplexed Addressing
The capacitance can act as a memory cell providing a simple circuit that
gives higher packing density at less cost.
The cell needs to
be charged
periodically (ms
order) even when
no memory read or
write.This is called
refreshing of cells,
characteristic of
Dynamic Random
Access Memory
(DRAM).

17. DRAM MEMORY CELL
Write and Read
● Parasitic capacitors C1 and C2
store 1-bit information.
● Consider, Q1 ON is storage of
1.Then C1 is charged to VDD and
C2 is discharged i.e. Q2 is OFF.
● If not accessed, C1 voltage keeps
Q1 ON and low C2 voltage keeps
Q2 OFF.
● However, C 1 charge leaks and
stored data may get lost.

18. ROM (READ ONLY MEMORY)
A Read Only Memory (ROM ) is memory device where binary information is
stored in certain interconnection pattern that is non-volatile.
Decoder-OR Circuit and ROM
Decoder – OR circuit that is equivalent to 8 x 3 ROM
A B C F
1
F
2
F
3
0 0 0 1 1 0
0 0 1 0 0 1
0 1 0 0 0 1
0 1 1 0 0 1
1 0 0 1 0 0
1 0 1 0 1 0
1 1 0 1 0 0
1 1 1 0 0 1

19. Programmable ROM (PROM)
PROM allows the user, instead of the manufacturer, to store the data.
An instrument called a PROM programmer stores the words by “burning in.”
An instrument called a PROM
programmer stores the words by
“burning in.”
The PROM programmer sends
destructively high currents through
diodes that are to be removed.
EXP:
To store 1001 (Y 3-0 ) in the
address location ABC = 000,
fuses at the cross points of
Y 2 and Y 1 in the A ̅ B ̅ C ̅ row
need to be burnt. Similarly
for other cross points
according to what is
stored in each address.

20. EPROM(ERASABLE), EEPROM(ELECTRICAL ERASABLE)
The erasable PROM (EPROM) uses MOSFETs.
All stored data can be erased by shining ultraviolet light
through a quartz window that releases all stored charges.
EEPROM IS VERY SLOW
Electrical charge is forced on floating gate. When electron
is present, threshold voltage is higher than normal which
is usually considered as logic ‘0’; else, logic ‘1’.
Flash Memory is further advancement of EEPROM. It is much faster as data writing is
in block (say, 512 bytes) instead of 1 byte at a time.

21. Conclusion:
➔ Study of various form of memory i.e. Primary and Secondary
memories, volatile and non - volatile.
➔ Memory cell addressing techniques - Linear addressing ,matrix
addressing.
➔ Reading and writing process- BJT based memory cells.
➔ RAM - random access, Volatile ,SRAM-refreshing not require &
DRAM- refreshing require.
➔ ROM-random access, non-volatile,PROM-Programmable : User can
program for single time ,EPROM,EEPROM .

22. References:
● Basic material contents of this are taken from lecture note of “Digital Electronics Circuit” ,
instructed by”Pro. Goutam Saha” , “Indian Institute of Technology Kharagpur”
● Donald P. Leach, Albert P. Malvino, and Goutam Saha, Digital Principles & Applications 8e,
McGraw Hill.
● https://www.digchip.com/datasheets/parts/datasheet/477/SN7489-pdf.php
● Sergei Skorobogatov (June 2002). "Low temperature data remanence in static RAM".
University of Cambridge, Computer Laboratory. Retrieved 2008-02-27.
● “Modern Digital Electronics” by- R P Jain 4th Ed. Tata McGraw Hill Private Limited ISBN:
978-0-07-06691-16
● “Digital Electronics: principle devices and applications” by- Anil K. Maini 2007 John Wiley &
Sons, Ltd. ISBN: 978-0-470-03214-5.
● “Digital Logic and Computer Design” by- M. Morris Mano, Person India Education Services
Pvt. Ltd. ISBN: 978-93-325-4252-5.

23. Thank you.

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