1. CMOS LNA
Hamid Kiabi
This project shows the design of a three stage CMOS
operational amplifier including a bias network in 0.35um CMOS
process.
The design specifications for this op-amp are:
1. AVo (DC Gain) > 60 dB
2. GBW > 1 MHz
3. PM (Phase Margin) > 45 degree
4. CL = 30 pF
5. PD < 2 mW
6. PSRR > 60 dB
Structure
The input stage is made up of the source-coupled pair transistors
(M1-M2) and the folded mirror transistors (M3-M4). The second
stage is a PMOS (M7) common source gain stage and the last
stage is a class AB push-pull output stage. Common source
transistors M11 and M12 provide a rail-to-rail output swing and
diode connected transistors (M8-M9) are used to bias the output
source follower transistors at class-AB. A Miller compensation
capacitor is added to the gain stage to ensure the stable
operation of the amplifier in closed loop. Bias network transistors
(M13-M15) supplies a bias current of 0.12 mA. The circuit has a
dual power supply of +2.5 and -2.5 volts.