1. Frank A. Civitano
civitano@sbcglobal.net
South Bay Area, CA (408) 823-4690 Cell
Summary Experienced VLSI hands-on product engineering manager; proven leader, communicator, problem-solver and
strategic/tactical planner introducing new and redesigned products into volume production
Skills
• Proven track record of managing multiple products through the complete product life cycle.
• Successfully delivered profitable products to market meeting market requirements, exceeded ROI objectives, and
introduced on time. Executed manufacturing releases of CMOS programmable logic, EPROM and FLASH memory,
and audio/video technologies.
• Very competent in operating all lab equipment typically found in semiconductor engineering labs
• Highly skilled in data mining and the use of statistical methods
• Excellent working relations with technical customer issues.
• Maintained knowledge in VLSI circuit and CMOS logic design fundamentals.
• Strong experience managing multiple concurrent and complex projects with multiple stakeholders.
• Project manager for offshore product, test and manufacturing engineers.
• Software experience in JMP, Galaxy, MBAYSE, Excel, Microsoft project, C++, MS Office
• Experience in personnel challenges (maintained employee loyalty and low turnaround).
• Excellent written and verbal communication skills (including presentation skills, excellent interpersonal and
relationship management skills).
Testers Teradyne, Megatest, Eagle, Credence and Genesis
Professional Texas Instruments Santa Clara, CA
Experience Product Engineer (contractor)
Nov, 2015 Product/Test/Reliability development engineering of GaN Power HEMTs. Performed data analysis using JMP
to statistical software. Completed qualification of LMG5200 Half Bridge Power Stage. Executing reliability quals of
present next generation TI Gan products. Reliability study of device characteristics and failure modes.
Feb, 2013 Transphorm, Inc. Santa Barbara, CA
to Staff Product Engineer
April, 2014 Gallium Nitride power device engineer working on discreet diodes and transistors. Brought up burn in production
in the Philippines. Brought up testing in the Philippines. Created numerous manufacturing specifications.
Contributed to the successful ISO9001 certification. Defined and documented a better procedure for purchasing
burn in boards. Responsible for tracking and dispositioning final test and reliability stresses; interfacing with
offshore test and burn-in engineers. Created control plans for various test and reliability operations.
Feb, 2012 EE Technologies Reno, NV
to Engineering Manager
Feb, 2013 Managed manufacturing, test and mechanical engineering as well as configuration management and
customer quoting. Strengthened the engineering team, transferred many of the quoting functions to
Mexico. Coordinated the introduction of many new automotive products in Mexico.
Brought up and debugged one of the first dual track iFLEX SMT lines manufactured. Optimized new product
introduction procedures. Ran the APQP meeting to evaluate new customer projects. Trained Engineers in
techniques of statistical, physical and electrical product analysis
March, 2008 Pacific Silkscapes Rancho Cordova, CA
To Program Manager/Co Owner
Feb, 2012 Responsible for P&L and financials of small business. Managed all manufacturing in company. Worked with
customers on various unique projects. Developed competitive pricing strategy. Redesigned website and
implemented ecommerce. Redefined company expanding available market to commercial and government
buildings to increase revenue by 35% per year. Identified critical needs to capture new markets such as the need
for fire retardant certification and obtaining a GSA schedule contract.
Page 1 of 3

2. March, 2006 Lattice Semiconductor San Jose, CA
to Sr. Product Engineering Manager
Feb, 2008 Product Development Engineering manager responsible for managing a team of eight engineers. I was responsible
for new product introduction, yield improvement, wafer and assembly budgets, product transfers, and QA of the
power models. Validation and characterization of 90 and 130nm Low Cost CMOS FPGAs (Lattice EC, ECP, ECP2 and
ECP2M) products were released to market on time. Held numerous design reviews and was instrumental in
debugging of critical new products. I participated as team member on Lattice’s power calculator tool development
and debug responsible for ECP products. Hired and managed two SERDES characterization engineers.
July, 2005 Intel Corporation Folsom, CA
to Operations Manager/Development Engineer
March, 2006 Folsom Development Lab operations manager in charge of 25 permanent and temporary
validation technicians, strategic and tactical planers, and an inventory control group (8 people) for Intel’s
microprocessor group. Responsible for providing a pool of resources to validate test programs and collect quality
data for product engineers, design engineers, development engineers, and the quality & reliability team. Directly
manages two test floor supervisors, one planning and IC manager and one validation engineer.
May 2001 LSI Logic Milpitas, CA
to Senior Product Engineering Manager
June 2005 Managed a group of up to 7 product engineers with the responsibility of reducing costs and
introducing new consumer products into volume production. Introduced set top box products and
DVD products into production.
• Hands on technical role leading Product Engineering
development teams in Santa Clara and Shanghai
• Successfully qualified & introduced new CMOS products to
market on time and within budget.
• Led cross-functional teams to improve sort & final test
corporate qualification guidelines that are currently being
used in the corporation.
• Represented engineering on quarterly business reviews with
offshore foundries.
• Trained and coached several new and experienced product
engineers both in the US and in Shanghai to be successful
product engineers.
• Performed reverse engineering on multiple competitor
products.
• Strong skills in debugging, characterizing, and qualifying new
products.
• Instrumental foundry relationships to qualify 0.13 and
0.18um technology test chips.
Mar. 1996 Xilinx, Inc. San Jose, CA
to Product and Test Engineering Manager
May 2001 Responsible for all XC17XXX and XC18XXX configuration serial PROMs.
• Drove the conversion of SPROM(18K to 256K) from TSMC’s fab in Taiwan to Seiko-Epson’s Fujimi plant.
• Brought up 16-site wafer sort probing at Fujimi.
• Converted all back-end final test programs from Credence STS to Genesis II testers.
• Upgraded from single site to multi-site testing at final test.
• Successfully introduced the XC17512 through XC1704 into production after debugging, characterization
and qualifications.
• Spearheaded a product engineering training program for the EPLD business unit that is still being used
today enlisting design, technology and manufacturing managers.
• Worked extensively with our fabrication foundries and assembly & test contractors.
Education
Page 2 of 2

3. Saint Mary’s College of California Moraga, CA
Masters of Business Administration
Santa Clara University Santa Clara, CA
Master of Science, Engineering Management
Polytechnic University of New York Farmingdale, NY
Bachelor of Science, Electrical Engineering
Page 3 of 3