1. Roger A. Spencer
Phoenix, AZ; 480-251-3652 (mobile); spencer.roger.a@gmail.com
Summary: Accomplished senior process engineer with thirty-one years experience in semiconductor
product, process and equipment management and development. Strong skills and experience in project
management and team leadership. Highly knowledgeable with semiconductor process equipment and
semiconductor metrology and inspection equipment. Objective is to obtain a rewarding position doing product,
process or equipment management or development and utilize extensive engineering training/experience and
educational experience. Skilled or strongly skilled with:
 Semiconductor Inspection Equipment
Operation and Applications
 Process Equipment Operation and
Applications
 Task Force and Team Leadership
 Semiconductor Manufacturing and Process
Development
 Yield Improvement and Data Analysis
Knowledge & Methods
 Equipment Product/ProcessInteractions
Intel Corp., Assembly Technology and Test Development (Package Assembly), Chandler, AZ
Finish Platform Lead for Finish Metrology and Inspection Module 2011 – 2016
Finish Platform lead driving completion of various platform related tasks with inspection engineers including
inspection recipe development and maintenance, design rule communications, providing collaterals, completing
development and production transfer deliverables, high volume factory training and inspection recipe matching,
metrology capability analysis, recipe transfer and UPH goals, documentation (Module Target Specs, Operational
and Loss code Specs, RFC’s, Whitepapers), mentoring junior engineers. Project manager for platform inspection
related activities, working groups and task forces. Received division recognition award (DRA) for leading eight
person materials team that improved component over-detection issues and associated manufacturing costs savings,
including $3M in component purchasing cost reductions with suppliers.
Platform Integration – Senior Engineer 2005 – 2011
Platform Integrator responsible for integrating materials, process, metrology and equipment to meet product
certification and transfer goals such as yield, quality, reliability, and MOR metrics. This included design, planning,
and execution of Design of Experiments for package/assembly path finding and development. Co-led platform
engineering team and received a DRA for assembly and packaging development of embedded array capacitor
(EAC). Was also integrator covering the Finish Inspection, Material Handling Systems and Media areas and
assisting with certification for all client products. Led various Finish/ICOS inspection tool related tasks and
projects to help enable various improved capabilities for including the implementation of a novel metrology method
on the ICOS metrology tool which also earned a DRA.
Process Integration – Senior Engineer 2004 - 2005
Led data analysis and data collection improvement effort for packaging process task force. This work helped the
team to improve yield from ~60% to ~90% in a 2 month period. Developed various WEB based analysis tools
which provided significant time savings and improved efficiency for module engineers. Led Unit Integrity/High
Value Inventory improvement effort to reduce Gross Unit Variance to acceptable levels for entire factory.
Intel Corp., Microchip Fab, Ocotillo, AZ
Defect Metrology – Senior Engineer / Team Leader / Acting Group Leader 2001 – 2004
Acting Group Leader for 8 month period of 4 engineers and 5 technicians in the Fab Defect Metrology group. Team
leader responsible for sustaining excellence and defect reduction of CPU and Chipset process. Led factory wide
defect teams and drove die yield improvement to achieve $6M per week in improved revenue. Led chipset ramp
readiness effort for defect metrology which contributed to record overall production ramp.

2. Roger A. Spencer
Phoenix, AZ; 480-251-3652 (mobile); spencer.roger.a@gmail.com
Previous experience:
Intel Corp, Senior Defect Metrology Engineer
Responsible for Fab-to-Fab transfer of defect inspection process. Led a 15 member cross functional ramp readiness
team for the production ramp, trained and prepared junior defect engineers. Led a litho defect task force which
resulted in a significant yield improvement ($8M per week in improved revenue). Lead defect reduction engineer
for Digital Legacy process. Owned and sustained various inspection tools including Tencor Surfscan, Orbot
inspection tool and SEM. Led various defect reduction task forces and cross functional teams.
Digital Equipment Corp, Senior Defect Reduction Engineer / Supervisor/ Senior Process Development Engineer
Supervised engineers and technicians for defect reduction of back-end CMOS process. Team leader for backend
defect reduction of new 8” fab. Responsible for coordinating defect reduction activities in the backend CMOS
process from poly dielectric through passivation. Initiated and directed Digital’s first backend CMP (Chemical
Mechanical Planarization) process development project. Worked with CMP consumable supplier on product
improvement. Led the development of the Spin-on-Glass (SOG) planarization process for multilevel interconnect
for 0.75um CMOS process. Developed and directed the transfer of oxide etch processes and novel, electromigration
(EM) resistant metals for IC interconnects. Developed thin film deposition and thin film characterization techniques
for the fabrication of x-ray lithography masks. Designed, performed and analyzed DOE’s to achieve low stress
films. Initiated and directed University research project for novel thin film development (Diamond-like Carbon).
EDUCATION:
Bachelor of Science (BS) in Electrical Engineering and Materials Science & Engineering (dual major) ,
CORNELL UNIVERSITY, Ithaca, NY – Concentrated in semiconductor materials, fabrication and device physics,
developed instrument to measure voltage drops across solar silicon grains.
Masters of Business Administration (MBA), Babson College, Wellesley, MA - Concentrated in Finance and
Entrepreneurial Studies (co-wrote business plan for software service company idea).
PUBLICATIONS:
 “Advanced Inter-Metal Dielectric Deposition- A Comparative Analysis between ECR-CVD and
O3/TEOS”, A. Bose, R. Spencer, M. Garver, VMIC, 1993, p. 89.
 Internal Intel paper: “Advanced Defect Reduction Methods on the Endura 5500 PVD System”, Spring,
1999
 Internal Intel paper: “Defect Management System for Assembly-Test Automated Defect Analysis, Yield
Improvement and Excursion Reduction” -- Spring 2012