Jason E Stephens’ 2020 Resume/CV

1. Jason E. Stephens Essex Jct., VT * (845) 554-8430
jes_uo@me.com
www.linkedin.com/in/jestephens
Jason's Google Scholar Page
SUMMARY
Motivated professional with 12 years of experience working in Advanced Semiconductor Technology R&D, dedicated
and passionate to personal growth and education. Proven longevity, strong work ethic and relentless drive to be a
leader in the Semiconductor and related fields. Achieved highest technical level of Master Inventor, initiated into a
select group of professionals made up of only 0.5% in GF. Proven strong leadership skills through managing small
teams and driving large x-functional teams to create motivational and rewarding environments that lead to
transcending results. Established background in BEoL/MoL/FEoL integration & design, Pathfinding R&D, design
enablement, test site enablement, DCTO, Benchmarking, and technical leadership. Strong belief in enabling other
professionals through mentorship and counseling. Published academic author and inventor/co-inventor of 24 granted
US patents, currently having over 40 other patent applications in process. BEoL Technical Patent Advocate Co-Chair
for the Patent Review Board at GlobalFoundries.
EXPERIENCE
GlobalFoundries | Technology & Development - RF Division
RF Tech. Development Integration Engineer, BEoL - Senior Member of Technical Staff & Master Inventor
May 2019 – Present
• Responsible for MoL/BEoL development of new RF Technology offerings based on existing 180nm, 130nm &
90nm Node product offerings.
• Responsible for transferring 180/130nm Node development projects to sister fab in Singapore.
• Proposed a review and enhancement of internal R&D design-process risk analysis standards that would position
the group to introduce entirely new and complex technologies in the future. After management agreed, I began
working to redefine the BP for robust technology development procedures and tools. Specifically through
definition of Process Assumptions documentation standards, risk assessment standards and methodologies for
Design-Process interactions, such as Monte-Carlo simulation package for “2D, multi-body, computations analysis
and Basic templates for 1D calculations of process-deign interactions.
Apple, Inc | Manufacturing-Design Operations - Display and Sensors
Quality Engineer – Technology Operations
March 2018 – May 2019
• Manufacturing Ops DRI for Apple Watch Display Module - OLED/TFT display, optical correction films, polarizer
film, touch sensor, Cu Glass, hinge flex with drivers & assembly of components into the final top display module.
As a DRI, I:
• Gave bi-Weekly updates to executives on Manufacturing status & current issues RCA & Resolution.
• Lead teams of vendors to define and implement operational procedures, BKMs & determination of defect
phenomenon RC mechanisms and implementation of best solution.
• Owned Maintenance, development, and application of a complex, in-house, 100,000+ line-of-code Matlab
(& Python) program. This tool queried millions of data points from multiple critical display and electrical
parameters of the OLED/TFT/Driver Module optical tester and applied sophisticated computational
algorithms and statistical analysis to provide continuous visibility of every possible optical and cosmetic
Apple-standard. This enabled deep understanding of display performance with precise ability to isolate non-
optimal parameter mechanisms . This tool was also used to quickly isolate and resolve known & Unknown
display quality issues and defect events.
• Previous owner and original creator of this project left the company and transferred ownership to me,
a few weeks into the job, with the pressure that no other colleagues had working knowledge of the
actual code. I was challenged to learn and master all 100,000+ lines of code within 2 weeks in order
to troubleshoot any potential bugs and deliver display performance reports and trends by start of

2. ramp. I mastered the code and was able to isolate major bugs and rewrite pieces of code within 3
weeks, in time for ramp. Additionally, I added a few dozen new features and over 30,000 lines of
code within the first month which lead to the proactive unearthing of display optimization
opportunities and the first time ability to trace panel excursions to specific points in line.
• Manufacturing Ops DRI responsible for engaging with development teams on upcoming watch projects in order to
communicate manufacturing needs, challenges, and ever changing timelines back to Manufacturing ops
executives. A Key responsibility in this role was to plan & execute the ramp of new watch products into HV
Manufacturing on extremely tight, and dynamic, deadlines in a high pressure, high stakes environment.
Edwards Ltd | A Division of Atlas Copco - Semiconductor Division
Global Market Sector Manager – Semiconductor Process Technology
Nov 2017 – March 2018
• Responsible for leading a team of market experts, focusing on different semiconductor process areas, to develop
and track the Semiconductor Process Technology sector technical forecast and annual operational plan.
• Worked with Global Product Managers, Regional Account Teams and Logic/Memory MSM to ensure execution of
annual operational plan to meet the business unit and growth/profitability targets.
GlobalFoundries - Pathfinding DTCO Technology Enablement
Next-Gen Tech Pathfinding & Enablement Team - Senior Member of Technical Staff & Master Inventor
July 2017 – Nov 2017
• Responsible for developing components of experimental Process Design Kits (PDK), with a scope covering Pcell
development, LVS, PEX, decomposition and DRC deck development, engineering place and route tooling, DTCO
evaluation/analysis, benchmarking and final technology definition for 5NM and 3NM nodes.
• Drive/collaborate with pathfinding core team members to define and evaluate new technology integrations &
features, scaling boosters & design architectures through pre-PDK PPAC analysis, design-to-technology evaluation/
analysis (e.g. DTCO) to determine the optimal technology definition for 5NM and 3NM nodes.
• Develop an agile automation infrastructure platform for rapid prototyping of “Pre-PDK new technology elements
to develop and generate PDK components for early technology performance analysis.
GlobalFoundries - Advanced Technology Development
7LP BEoL Integration Pathfinding Technical Lead - Senior Member of Technical Staff & Master Inventor
October 2015 - July 2017
• 7NM BEoL Integration exploration, definition, proof of concept, test Site content definition, development, and
overall technical leadership. Technology demonstration aligned with GlobalFoundries M1-M6 milestone exit
criteria and timeline. DTCO interaction in a technology and integration leadership role, working in partnership
with teams from design, enablement, customer facing groups, characterization, rel., IE. and worked with DTCO
and Customer input to define important test site content. Presented program updates and technical briefings to
executives, management, and engineering teams.
• 7LP LP BEoL Owner/DRI: (LP BEoL Technology definition/implementation/coordination)
‣ Delivered the first 7LP BEoL technology demonstration enabling a GLOBALFOUNDRIES 7LP BEoL process
and delivering SRAM 1M yield by 2016 year end. Process demonstration completed 1 month ahead of the
target date of end of 1H16.
‣ Lead and executed all facets of R&D, w/ 3-4 full time integration engineers, delivering a process
demonstration and initial integration process package with critical PAs within 5% of nominal targets and
identification of Top5-10 issues with development plans to resolve and understand the top issues by 1H16.
• 7LP HP BEoL GoTo Owner/DRI: (GoTo Technology definition/implementation/coordination)
‣ Lead a x-functional team of 40 + engineers, with 5 direct reports within the integration team (not responsible
for final GPM reviews). Technical lead, responsible for project plan, road map definition, and pathfinding/
definition/delivery of the company’s technology development program strategy & schedule for a HP 7LP
GoTo BEoL technology offering, from pathfinding all the way to our first customer MPW tapeout readiness
milestone.
‣ Acted as the program manager and technical lead to define, create and deliver through collaboration with all
7LP teams, the overall program plan and strategy, from ground zero and pathfinding to Si demonstration and
yield ramping, all the way to PDK intercepts for customer MPW and product tapeouts.

3. ‣ Lead and executed the delivery of a reduced cost technology definition (~100 less process steps than the
current 7LP BEoL POR process, and the reduction of 4 masks) which enabled GLOBALFOUNDRIES to be
competitive with TSMC and the foundry world.
GlobalFoundries - Advanced Technology Development
Design Rule & Technology Development Lead - Member of Technical Staff & Senior Engineer
2010 - 2015
• Provided innovative process integration and design architecture solutions that enabled best in class, foundry
competitive, technology platform for 10NM.
• Team leader for development and integration of the foundry industry's first use of Self-Aligned Double Patterning
(SADP) at the metal interconnect level for integrated circuits.
• Successfully developed and implemented customer friendly PDK and design rule solutions for SADP interconnect
designs.
• Delivered technology milestones on schedule and developed SADP design-to-mask methodologies & tools.
• Championed Design-to-Process Co-optimization efforts to address new challenges in enablement methodologies
that resulted from increased use of multi-patterning processes in FEoL, MoL, and BEoL modules which resulted in
competitive std. cells, optimal pin accessibility for optimal cell utilization, innovative solutions to cell boundary
conditions, and ultimately leading to best in class P&R results.
• Developed new and innovative methodologies to address/fix issues with the quality of triple and double patterned
colorless design decomposition.
• Development of a virtual process flow for an SADP metal interconnect module to provide early evaluation and
studies of known limitations and risks.
• Senior Engineer (2010-2013)
‣ Lead 14NM/10NM BEoL and MoL design rule development for advanced technologies within ISDA/JDA
consortium and worked collaboratively in a multi-company/multi-cultural environment with many
departments, from patterning/OPC/UP/Reliability to design/drc/device and customers.
‣ Consistently delivered innovative and competitive technology solutions on aggressive timelines.
‣ Played key role in the development of double patterned LELE design rules and colorless rules integration.
‣ Played a key role in enabling a competitive 9T/7.5T Std. Cell Library through the invention and
implementation of non-standard limiting parameter (NSLP) methodologies (see patent).
ON SEMICONDUCTOR / LSI
Device Integration Engineer & In-Line Yield Engineer
2005 - 2009
EDUCATION
University of Oregon, Eugene, OR - Master of Science - Applied Physics
2004 - 2005
Earned a Master of Science in Applied Physics.
Southern Oregon University, Ashland, OR - Bachelor of Science - Physics & Mathematics Minor
2000 - 2004
Earned a Bachelor of Science in Physics with a minor in Mathematics.

4. SKILLS
• New Product Introduction and Validation; Path-finding; Semiconductor device Technology Definition &
Development, Process/Device Integration, Design, and Enablement; Design-Technology-Co-Optimization.
• Adept at numerous computer applications, software, and project management.
• Design Rule development, Design for Manufacturing, Physical Design simulation and emulation, DRC, Process
Assumption calculations/definition and validation, Monte Carlo Simulation, multi-patterning PDK enablement,
Design of Experiments, SPC, Characterization, metrology, PPA, P&R, PEX, TCAD, Matlab & Python.
• Experienced use & application of quantitative research methods, mathematical and statistical principles, statistical
theories & methods, and principles of device physics to technology development.
• Experienced at writing technical papers, reports, and patent disclosures as well as in communicating research/data
through technical reports, presentations, and other methods.
*references, patent list, and journal articles available upon request