More Related Content Similar to Achieving Power Noise Reliability Sign-off for FinFET based Designs (20) Achieving Power Noise Reliability Sign-off for FinFET based Designs1. 6/23/2014 © 2014 ANSYS, Inc. 1
Achieving Power Noise Reliability Sign-off for
FinFET Based Designs
Design Automation Conference 2014
2. 6/23/2014 © 2014 ANSYS, Inc. 2
FinFET Advantages
• Lower Leakage
• Higher Driving Current
• Lower Operating Voltage
• Higher Device Density
Source: ARM FinFET study, 2013
FinFET Delay Characteristics Study
3. 6/23/2014 © 2014 ANSYS, Inc. 3
FinFET Migration Challenges
65nm
• Static IR
• Dynamic IR
40nm
• Low Power
• Leakage Opt.
• Chip + Package
• Static IR
• Dynamic IR
28nm
• Reliability
• Power/Signal EM
• Low Power
• Leakage Opt.
• Chip + Package
• Static IR
• Dynamic IR
20nm
• Advanced
Reliability
• ESD
• Power/Signal EM
• Low Power
• Leakage Opt.
• Chip + Package
• Static IR
• Dynamic IR
16nm
• Thermal Impact
• Chip-Pkg Co-design
• Advanced Reliability
• ESD
• Power/Signal EM
• Low Power
• Leakage Opt.
• Chip + Package
• Static IR
• Dynamic IR
Increasing number of checks for
advanced technology nodes
Sign-off mandates advanced checks for
the FinFET nodes
4. 6/23/2014 © 2014 ANSYS, Inc. 4
FinFET Migration Implications: DvD, Noise
Design / Process Changes Impact
Lower supply voltage, VTHRESHOLD
Significantly higher L di/dt noise
Less noise margin
Bigger impact on clock jitter, timing
More current in same layout area
Higher Idrive (~1.25X each generation)
Complex metallization, via structures
Accurate extraction, rule handling
Significantly higher capacity requirements
More number of metal layers (top, bottom)
5. 6/23/2014 © 2014 ANSYS, Inc. 5
FinFET Migration Implications: EM & ESD
Design / Process Changes Impact
Degraded via EM limits (0.7X reduction in every
generation)
Via and wire EM will limit routing length or driver size
Increased self heating Model CPS thermal effect on local EM
Degraded diode protection
Bigger ESD devices, better placement guidance
Higher sensitivity to ESD events (wire and via burnout)
Degraded Interconnect Reliability
6. 6/23/2014 © 2014 ANSYS, Inc. 6
Technology Enablement for FinFET Processes
Netlist/Simulations
• Fin device recognition
• Dummy device modeling
• TMI model handling
GDS/Extraction
• Extraction of FEOL metal stack
• Double/triple patterning support
• Pseudo/complex via support
EM/ESD Checks
• Complex EM rule support
• EM & self heat for all metals
• Interconnect failure for ESD
7. 6/23/2014 © 2014 ANSYS, Inc. 7
Foundry Certified for FinFET Processes
Certified for TSMC 16nm v1.0 and Intel Custom Foundry 14nm
• Resistance correlation
• EM Rule handling
• IR/DvD extraction and analysis
Unique metal architecture
• Special metal layers
• Complex via structures and shapes
• Diffusion as interconnect structures
Enhanced modeling
• Dummy devices
• Vertical resistance
• Double patterning
Complex EM, ESD
• Current-direction, metal topology based
• Width, temperature, self-heat, etc
• Pseudo-via, RMS, etc.
8. 6/23/2014 © 2014 ANSYS, Inc. 8
FinFET Signoff Solution
Power Grid Connectivity
Power and Signal Reliability
Advanced Power Noise Signoff
Integration of Multiple IP’s
Full Chip Capacity
Distributed Machine Processing
Silicon Correlated
System/Package Impact on Die
Pico-second Resolution
9. 6/23/2014 © 2014 ANSYS, Inc. 9
Connectivity Checks
Connectivity
Grid weakness
Static IR
Missing vias
Grid weakness check
Resistance checks
Power/Ground balance
Switch placement
Pad placement
IR drop checks
High power density checks
Highlights regions with missing vias
(User can click and zoom into RH)
Missing Via Checks Resistance / Grid Weakness Checks
10. 6/23/2014 © 2014 ANSYS, Inc. 10
Reliability Checks
Reliability
EM
Thermal
ESD
Power EM (AVG)
Signal EM (RMS/PEAK)
Chip thermal modeling
Thermal annotation for EM
System thermal modeling
Clamp placement check
Cross domain checks
Res. checks (HBM/MM)
Current-density checks
IP CDM checks
Power EM Pad Cur Map
Power EM, pad EM limits, switch IDsat
checks, etc.
Power EM/Current Density
Signal EM analysis Driver checks
Data and clock signal EM, driver checks
Signal EM/Driver Current
11. 6/23/2014 © 2014 ANSYS, Inc. 11
Reliability Checks
Reliability
EM
Thermal
ESD
Power EM (AVG)
Signal EM (RMS/PEAK)
Chip thermal modeling
Thermal annotation for EM
System thermal modeling
Clamp placement check
Cross domain checks
Res. checks (HBM/MM)
Current-density checks
IP CDM checks
Temperature-aware EM analysis
Thermal Profile Post Thermal EM
Thermal Annotation for EM
Current Density ESD Failure
ESD Checks
12. 6/23/2014 © 2014 ANSYS, Inc. 12
Power-Noise Sign-off
Power Noise
Sign-off
DvD noise
Low Power
Impact on timing
Vectorless analysis
Vector analysis
Functional/test modes
Multi-cycle vectorless
Detailed package impact
Accurate IP impact
Multi-domain analysis
Power-up/dn analysis
Scan Mode Analysis
Scan Vectorless
Scan VCD
Demand current
Scan DvD
Vectorless / Vector DvD
Custom Digital
(VectorLess)
Memories
(VectorLess or
Vector-based)
Analog
Block
(Vectored)
13. 6/23/2014 © 2014 ANSYS, Inc. 13
Power-Noise Sign-off
Power Noise
Sign-off
DvD noise
Low Power
Impact on timing
Vectorless analysis
Vector analysis
Functional/test modes
Multi-cycle vectorless
Detailed package impact
Accurate IP impact
Multi-domain analysis
Power-up/dn analysis
Package-Aware Chip Simulation Chip-Aware Package Optimization
14. 6/23/2014 © 2014 ANSYS, Inc. 14
Power-Noise Sign-off
Power Noise
Sign-off
DvD noise
Low Power
Impact on timing
Vectorless analysis
Vector analysis
Functional/test modes
Multi-cycle vectorless
Detailed package impact
Accurate IP impact
Multi-domain analysis
Power-up/dn analysis
Impact on Timing
Timing Bottleneck Map DVD Map
Timing Hotspot
Power Up/Dn Analysis
15. 6/23/2014 © 2014 ANSYS, Inc. 15
FinFET Sign-off Coverage Requirements
Connectivity
Reliability
Power Noise
Sign-off
Grid weakness
Static IR
Missing vias
Grid weakness check
Resistance checks
Power/Ground balance
Switch placement
Pad placement
IR drop checks
High power density checks
EM
Thermal
ESD
Power EM (AVG)
Signal EM (RMS/PEAK)
Chip thermal modeling
Thermal annotation for EM
System thermal modeling
Clamp placement check
Cross domain checks
Res. checks (HBM/MM)
Current-density checks
IP CDM checks
DvD noise
Low Power
Impact on timing
Vectorless analysis
Vector analysis
Functional/test modes
Multi-cycle vectorless
Detailed package impact
Accurate IP impact
Multi-domain analysis
Power-up/dn analysis