SOFICSformerly known as Sarnoff Europe<br />July 2009<br />Pieter Donck<br />
TakeCharge used by &gt;30 customers and licensees<br />IDM – Fabless – Foundry partners<br />Sofics © 2009<br />Proprietar...
TakeCharge ESD implemented in &gt;500 ICs<br />TakeCharge milestones<br />Since 2002: &gt;500 volume production ICs report...
TakeCharge complements ESD portfolio<br />TakeCharge: complementary solutions<br />Augment available portfolio<br />Focus ...
TakeCharge Engagement models<br />ESD test service<br />ESD analysis or qualification for your ASIC<br />ESD consulting se...
TakeCharge ServiceESD TEST SERVICE<br />Sofics © 2009<br />Proprietary & Confidential<br />6<br />
SOFICS has a state-of-the-art ESD lab<br />Fully equipped ESD test lab<br />HBM ANSI/ESDA and JEDEC on packaged dies<br />...
ESD test equipment <br />ESD related equipment<br />HBM, MM, latch-up: 	Keytek Mk.2<br />TLP: 		BEI 4002 TLP: 75ns and 100...
ESD, DC Analysis<br />TLP, VFTLP, DC (parametric, curve tracer)<br />Wafer or bare dies<br />ESD Qualification<br />HBM, M...
TakeCharge cells<br />Sofics © 2009<br />Proprietary & Confidential<br />10<br />
TDK cells – Product proven ESD clamps<br />Approach<br />Purchase selected ESD clamps<br />Single clamp or single voltage ...
TDK ESD cells for foundry processes <br />Silicon and product verified ESD clamps:<br />TSMC<br />350nm HV – 180nm – 130nm...
TDK cells – Topology / clamp types<br />Clamp types available<br />Core protection<br />IO clamps<br />Input protection<br...
Key benefits with TakeCharge solutions<br />Key technical benefits<br />Area efficient solutions<br />Win business, volume...
Calculation tool<br />Sofics © 2009<br />Proprietary & Confidential<br />15<br />
Straightforward path to optimized ESD solutions<br />TakeCharge ESD calculation tool<br />Clear visualization & navigation...
Calculation tool<br />Growing difficulty for ESD protection<br />Advanced CMOS, Complex System-on-Chip designs<br />Beyond...
Advanced CMOS<br />Sofics © 2009<br />Proprietary & Confidential<br />18<br />
TakeCharge – experience in advanced CMOS<br />SOFICS experience in advanced IC applications<br />SerDes IO’s in FPGA’s: 		...
TakeCharge – flexible ESD solutions<br />TakeCharge ESD protection<br />Tunable trigger voltage Vt1<br />External, exchang...
Universal power clamp<br />Sofics © 2009<br />Proprietary & Confidential<br />21<br />
ESD protection for High Voltage applications<br />Various ESD protection clamps in use (overview 1/2)<br />HV NMOS: RC-Big...
ESD protection for High Voltage applications<br />Various ESD protection clamps in use (overview 2/2)<br />Zener diode: re...
Contact Us<br />TakeCharge Technology<br />Bart Keppens 		bkeppens@sofics.com<br />Benjamin Van Camp		bvancamp@sofics.com<...
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Sofics, experts in ESD on chip protection

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Sofics Linkedin

  1. 1. SOFICSformerly known as Sarnoff Europe<br />July 2009<br />Pieter Donck<br />
  2. 2. TakeCharge used by &gt;30 customers and licensees<br />IDM – Fabless – Foundry partners<br />Sofics © 2009<br />Proprietary & Confidential<br />2<br />
  3. 3. TakeCharge ESD implemented in &gt;500 ICs<br />TakeCharge milestones<br />Since 2002: &gt;500 volume production ICs reported<br />Product proven in 8 CMOS generations, BiCMOS, BCD…<br />Partnerships with major and specialty foundries<br />July 2008: 40nm ESD solutions validated in silicon<br />Sofics © 2009<br />Proprietary & Confidential<br />3<br />
  4. 4. TakeCharge complements ESD portfolio<br />TakeCharge: complementary solutions<br />Augment available portfolio<br />Focus on custom or specialty requirements<br />High speed applications<br />Low leakage for green/mobile applications<br />High ESD performance requirements<br />Special analog requirements<br />Small silicon area clamps<br />Full chip implementation support<br />Sofics © 2009<br />Proprietary & Confidential<br />4<br />Standard logic<br />ESD-circuit matching<br />Low capacitance<br />High ESD requirement<br />Interdomain / core issues<br />
  5. 5. TakeCharge Engagement models<br />ESD test service<br />ESD analysis or qualification for your ASIC<br />ESD consulting service <br />Solve ESD issues, increase ESD confidence, quickly!<br />TakeCharge Design Kits (TDK) <br />Comprehensive solution set for 180nm – 40nm<br />Optimize ESD independently from SOFICS.<br />TakeCharge Technology transfer<br />Consistently realize first-time-right, optimized, robust ESD design<br />Independently migrate ESD solutions to multiple processes<br />Sofics © 2009<br />Proprietary & Confidential<br />5<br />
  6. 6. TakeCharge ServiceESD TEST SERVICE<br />Sofics © 2009<br />Proprietary & Confidential<br />6<br />
  7. 7. SOFICS has a state-of-the-art ESD lab<br />Fully equipped ESD test lab<br />HBM ANSI/ESDA and JEDEC on packaged dies<br />MM ANSI/ESDA and JEDEC on packaged dies<br />Latch-up JEDEC on packaged dies<br />TLP (2) on packaged and bare dies<br />VF-TLP on bare dies with high current RF probes<br />Probe stations (3)<br />DC leakage and IV tracing on packaged and bare dies<br />Solid state pulsing on packaged and bare dies<br />Thermo chuck<br />Test boards and sockets for various packages<br />Sofics © 2009<br />Proprietary & Confidential<br />7<br />
  8. 8. ESD test equipment <br />ESD related equipment<br />HBM, MM, latch-up: Keytek Mk.2<br />TLP: BEI 4002 TLP: 75ns and 100ns pulse width<br />VF-TLP: BEI 4012 VF-TLP: 1 ns, 2ns, 5ns, 10ns pulse width<br />DC / latch-up equipment<br />Parametric analyzer: Keithley 4200<br />Curve tracer: Tektronix Type 576<br />High temperature Micromanipulator<br />Sofics © 2009<br />Proprietary & Confidential<br />8<br />
  9. 9. ESD, DC Analysis<br />TLP, VFTLP, DC (parametric, curve tracer)<br />Wafer or bare dies<br />ESD Qualification<br />HBM, MM, TLP, Latch-up<br />Packaged samples<br />DIL16 - DIL48<br />QFP208<br />Sofics © 2009<br />Proprietary & Confidential<br />9<br />
  10. 10. TakeCharge cells<br />Sofics © 2009<br />Proprietary & Confidential<br />10<br />
  11. 11. TDK cells – Product proven ESD clamps<br />Approach<br />Purchase selected ESD clamps<br />Single clamp or single voltage domain<br />GDSII layout file, LVS netlist<br />1 page description (connection guidelines, ESD behavior)<br />Dual diode included for ‘domain’ purchases<br />Customization services available<br />Increase ESD performance<br />Change metallization<br />Change aspect ratio<br />Cells for custom requirements available on request<br />Customer integrates ESD clamps<br />Implementation review services available<br />Sofics © 2009<br />Proprietary & Confidential<br />11<br />
  12. 12. TDK ESD cells for foundry processes <br />Silicon and product verified ESD clamps:<br />TSMC<br />350nm HV – 180nm – 130nm – 90nm – 65nm – 40nm<br />UMC<br />180nm HV – 130nm – 65nm<br />Tower<br />130nm – 350nm<br />Other <br />Fujitsu 65nm – Epson 130nm<br />Chartered 65nm: qualification on-going<br />Various other cells available<br />Other voltage domains, process nodes, or foundries<br />Sofics © 2009<br />Proprietary & Confidential<br />12<br />
  13. 13. TDK cells – Topology / clamp types<br />Clamp types available<br />Core protection<br />IO clamps<br />Input protection<br />Output protection<br />IO protection<br />Special cells<br />Low capacitive<br />Overvoltage tolerant (OVT)<br />Area information<br />Includes guard bands and reverse diode<br />‘Both directions’ includes 2 local clamps and dual diode<br />Sofics © 2009<br />Proprietary & Confidential<br />13<br />VDD<br />IO<br /> Circuit<br />PAD<br />RISO<br />IO<br /> Circuit<br />VSS<br />
  14. 14. Key benefits with TakeCharge solutions<br />Key technical benefits<br />Area efficient solutions<br />Win business, volume and margins<br />Scalable ESD performance <br />Reach any ESD requirement<br />Low leakage and Latch-up immune<br />No interruption of normal operation<br />Tunable trigger voltage and current<br />Complete solution package. <br />Protection of Analog IO’s<br />No process changes for ESD solutions<br />‘Over voltage’ and ‘under voltage’ tolerant options<br />Optimization through calculation tool<br />Sofics © 2009<br />Proprietary & Confidential<br />14<br />
  15. 15. Calculation tool<br />Sofics © 2009<br />Proprietary & Confidential<br />15<br />
  16. 16. Straightforward path to optimized ESD solutions<br />TakeCharge ESD calculation tool<br />Clear visualization & navigation<br />Design guidance<br />Automatic w/ pre-selections<br />Design window calculation(any circuit-to-be-protected)<br />Performance check<br />Design optimization<br />Full IC consideration<br />Trade offs<br />Capacitance, area, leakage,bus resistance…<br />Sofics © 2009<br />Proprietary & Confidential<br />16<br />
  17. 17. Calculation tool<br />Growing difficulty for ESD protection<br />Advanced CMOS, Complex System-on-Chip designs<br />Beyond standard ESD requirements<br />Analog design requirements (capacitance, leakage)<br />Solutions: ESD design tool<br />Step-wise, easy to use GUI<br />Easily compare different protection strategies<br />Optimize functional – ESD trade-offs<br />Based on on-Chip ESD IP blocks<br />Customized per technology node and foundry<br />Silicon proven IP in 8 CMOS generations and &gt;500 IC’s<br />Sofics © 2009<br />Proprietary & Confidential<br />17<br />
  18. 18. Advanced CMOS<br />Sofics © 2009<br />Proprietary & Confidential<br />18<br />
  19. 19. TakeCharge – experience in advanced CMOS<br />SOFICS experience in advanced IC applications<br />SerDes IO’s in FPGA’s: 180nm – 40nm<br />10Gbps Optical communications: 130nm – 180nm<br />HDMI: 130nm<br />USB 2.0: 130nm – 90nm<br />Serial ATA: 130nm – 90nm<br />ASICs: 180nm – 65nm<br />...<br />Sofics © 2009<br />Proprietary & Confidential<br />19<br />
  20. 20. TakeCharge – flexible ESD solutions<br />TakeCharge ESD protection<br />Tunable trigger voltage Vt1<br />External, exchangable trigger elements<br />Tunable holding voltage Vhold<br />Latch-up immunity<br />Tunable failure current It2, Imax<br />Any ESD specification possible<br />Low dynamic resistance Ron<br />Design margin for full chip ESD<br />Low capacitive<br />For high speed IOs<br />Low leakage <br />Sofics © 2009<br />Proprietary & Confidential<br />20<br />Current<br />Vdd<br />Vmax<br />Vburn-in<br />It2<br />Imax<br />Damage<br />of<br />IO <br />or core<br />RON<br />Voltage<br />Vhold<br />Vt1<br />
  21. 21. Universal power clamp<br />Sofics © 2009<br />Proprietary & Confidential<br />21<br />
  22. 22. ESD protection for High Voltage applications<br />Various ESD protection clamps in use (overview 1/2)<br />HV NMOS: RC-BigFet<br />Large silicon area, high leakage<br />Tuning is difficult for high voltage processes<br />HV NMOS bipolar: double snapback<br />Low ESD robustness – non-uniform ESD current conduction & degradation<br />Large silicon area, high leakage<br />Latch-up due to deep snapback<br />HV PMOS bipolar: no snapback<br />Large silicon area, high leakage<br />Limited portability between fabs and processes<br />Large voltage drop during ESD stress<br />Sofics © 2009<br />Proprietary & Confidential<br />22<br />
  23. 23. ESD protection for High Voltage applications<br />Various ESD protection clamps in use (overview 2/2)<br />Zener diode: reverse diode conduction<br />Large silicon area, high leakage<br />Large voltage drop during ESD stress<br />High BD voltage – small margin for core protection<br />HHI-SCR: SOFICS proprietary<br />High ESD robustness in smallest area<br />Tunable trigger conditions (Vt1, It1, Ihold)<br />Latch-up free up-to predefined current level<br />Universal HV power clamp: SOFICS proprietary<br />High ESD robustness in smallest area<br />Tunable device for triggering and clamping<br />Latch-up immune for all current levels<br />Sofics © 2009<br />Proprietary & Confidential<br />23<br />AREA COMPARISON<br />Zener100%<br />PMOS50%<br />SOFICS10%<br />- HHI-SCR<br />- Universal HV clamp<br />
  24. 24. Contact Us<br />TakeCharge Technology<br />Bart Keppens bkeppens@sofics.com<br />Benjamin Van Camp bvancamp@sofics.com<br />TakeCharge Business<br />Pieter Donck pdonck@sofics.com<br />Koen Verhaege kverhaege@sofics.com<br />Sofics<br />Brugsebaan 188A, B-8470 Gistel, BELGIUM<br />(tel) +32-59-275-915, (fax) +32-59-275-916<br />www.sofics.com<br />Sofics © 2009<br />Proprietary & Confidential<br />24<br />

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