#RESUME

1. ANAND P P
Parakkatt Parambil H Po Puthuppally Tirur, Malappuram(Dist) , Kerala (state) , INDIA - 676102
+91-9746924414 ppanand74@gmail.com
OBJECTIVE
Seeking a challenging and innovative job where I can serve with the best of my capabilities and to continually
upgrade my knowledge and skills in the process of contributing to the organizational goals
EDUCATION
Bachelor of Technology in Electrical and Electronics Engineering 2012 - 2016
College Of Engineering Chengannur , affilated to Cochin University Of Science and Technology , Chengannur .
CGPA : 6.56 / 10
Intermediate - Kerala State Board 2010 - 2012
Fathima Matha Higher Secondary School , Tirur , Malappuram(Dist) , Kerala - 75.6 %
Class X - AISSE ( CBSE ) 2009
Kendriya Vidyalaya Malappuram , Malppuram (Dist) , Kerala - 75.6 %
PROJECTS
1 . Power controller for Inverter charging. Dec 2014 - Apr 2015
Designed and developed a Power controller for inverter charging, which would de-energize the battery of the in-
verter and reconnect it to the power supply during peak and o-peak hours respectively. This substantially would
reduce the load during peak hours.
2 . Load management on smart grid using Zig-Bee. Dec 2015 - Apr 2016
Smart Grid is currently the most sought after the technological concept of the present day power generation and
distribution sector. The proposed system deals with the management of electrical load using the latest ZigBee
communication technology. Here it concerns with the management of load connected in a Smart Grid, to ensure
uninterrupted supply to critical services. This system deals with the distribution control centre and consumers.
3 . Sentimental Analysis on demonetization based on twitter data using BIG DATA tools Sept 2016 – Feb 2017
https://github.com/anand2201/sentiment-analysis-on-demonetization-using-pig .
4 . Digial Code Lock Using VHDL and Implemetation using FPGA spartan 3A June 2019 – Aug 2019
The project is built around four D- Flipops. The clock pins of the four ip-ops are connected to the 4bits which
is the password/key of the lock. The correct code sequence for energization of D- Flipops is realized by clocking
points of 4bits of password in that order. The six remaining inputs are connected to the reset circuit which resets
all the ip-ops. Touching the keypad switches correctly (i.e...The correct password) briey pulls the clock input pin
high and the state of the ip-op is altered. Thus, if the correct clocking sequence is followed then high output
occurs which unlocks the system.
CERTICATIONS
1 . Advanced Diploma in Big-Data Analytics, National institute of Electronics and information technology ,
calicut ( NIELIT calicut) Sept 2016 – Feb 2017
6-month Advanced Diploma course which primarily focus on the data science tools like Java, Python, R, MySQL,
Hadoop and its frameworks PIG, Apache Hive, Sqoop, H Base.

2. 2 . PG Diploma in VLSI, SMECLABS Cochin June 2019 – Aug 2019
3-month PG Diploma course focused mainly on languages like VHDL , VERILOG , SYSTEM VERILOG , FPGA
(design and architecture) , CMOS basic , Analog layout using Tanner (EDA Tool) , Cadence Virtuoso (EDA Tool).
SOFTWARE TOOLS
HDLS VHDL, Verilog , System-Verilog , FPGA spartan series
EDA Tools Cadence Virtuoso , DRC , LVS , PEX , ERC , Verification : Assura and Calibre
Platforms Model-Sim, Xilinx ISE .
PERSONALITY TRAITS
Technical Expertise cmos design , Analog layout Design.
Interest and Hobbies Drawing , Football , Movies , Music , Political Science , Technological Innovation.
PERSONAL PROFILE
Date of Birth 22 January 1993
Languages known English, Malayalam and Hindi.
LinkedIn linkedin.com/in/anand-p-p-35a642180
Alternative Number +91 - 9383461993
DECLARATION
I hereby declare that the above-provided information is true to best of my knowledge .