Actively Seeking Opportunity in VLSI& Semiconductor Industry. Looking for a challenging career to enhance my professional ability, skills and technical knowledge and growth in Semiconductor industry.
Actively Seeking Opportunity in VLSI& Semiconductor Industry. Looking for a challenging career to enhance my professional ability, skills and technical knowledge and growth in Semiconductor industry.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
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Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...
Mansooralikhan vlsi
1. MANSOORALIKHAN A
Email: mansooralikhan2016@gmail.com
Mobile: +91-9087503679
OBJECTIVE
To pursue a challenging career in an organization that offers continuous building of
conventional skills, innovative ingenuity and promotes exposure to the recent technologies.
ACADEMIC DETAILS
COURSE INSTITUTE YEAR PERCENTAGE/
CGPA
M.E
(VLSI Design)
College of Engineering
Guindy(CEG),Anna University 2014-2016 7.20
B.E
(ECE)
Anna University of Technology,
Trichy 2010-2014 7.34
HSC Indian Matriculation Higher
Secondary School
2008-2010 92.9%
SSLC Government Higher Secondary
School
2008 92.4%
TECHNICAL EXPOSURE
Programming Language : C, Verilog ,VHDL,RTL
EDA Tools : Cadence Virtuoso(180nm),Xilinx ISE Design Suite
Simulation Tools : MATLAB, LT Spice,Keil
AREA OF INTEREST
Digital Electronics
Digital System Design
ASIC Front End and Back End
Physical Design , RTL Design
RESEARCH AND PROJECTS
ME PROJECT :
“Segmentation Based Energy Efficient Approximate Multiplier for
Digital Signal Processing”
2. OBJECTIVE :
The purpose of this project is to design and construct low power, area ,energy
efficient multiplier. To reduce this energy consumption we apply new multiplication techniques
in the multipliers. The proposed multiplier compared with a precise multiplier can consume 58%
less energy. In the proposed multiplier architecture, the area has reduced compared to other
multiplier architectures which process same number of bits.
My work is to implement new multiplication technique in Xilinx ISE Design
Suite and Power, Area, Delay calculated by Cadence Virutoso 180nm tool.
BE PROJECT:
“A True Random-Based Differential Power Analysis Countermeasure
Circuit for an AES Engine”
OBJECTIVE :
The purpose of this project resolving a security problem on ring oscillators and
implementing a new architecture with self-generated true random sequence.The true random
based architecture is implemented with an AES in Xilinx ISE Design Suite tool.
RESEARCH PUBLICATION
My project has been published in the journal IJARECE(The
International Journal of Advanced Research in Electronics and Communication
Engineering) at Volume 5, Issue 3, March 2016
PERSONAL DETAILS
Date of birth : 10.06.1993
Sex : Male
Nationality : Indian
Marital Status : Single
Languages known : English, Tamil (Read and Write)
Address : 3/566,Marukkalam patti (village),Alapuram(po)
Pappireddipatti(Tk),Dharmapuri (Dt)-636904
DECLARATION
I hereby declare that all the above details furnished by me are true and correct
to the best of my knowledge and belief.
DATE :
PLACE: CHENNAI ( A. Mansooralikhan)
