Srivalli Siddavatam seeks a position as an electronic engineer where she can utilize her skills in VLSI and embedded systems. She has experience with MATLAB, ModelSim, and Xilinx software tools. She completed two industrial learning projects - designing adders for cryptography using ModelSim and Xilinx, and designing an efficient reversible multiply accumulate unit using Xilinx and ModelSim. She graduated from TRR Engineering College for Women with a B.Tech in electronics and communication engineering.

1. CAREER
OBJECTIVE
 To secure a best position where I can effectivelycontribute my skills as Electronic
Engineerwith good knowledge in VLSI and Embeded Systems.And Having knowledge
in Softwares Matlab, Modelsim And Xilinx
Skills Software Tools :
Languages :
MATLAB v6.4b, Model Sims, Xilinx’s IES v14.7
Verilog, VHDL
Academic
Experience
INDUSTRIAL LEARNING (MINIPROJECT PROGRAM) [Sep’ 2014]
Project #1 : Design Of Adders For CryptographyApplication
ProjectOrganization:
 KREST TECHNOLOGIES
ProjectTechnology & Tool Stack :
 Softwares : ModelSim ISEv6.4B
 Operating System: Windows 7
 Documentation Tools: MS-Office 2003
ProjectDescription:
 The binary adder is the critical element in most digital circuit designs including
digital signal processors (DSP) and microprocessor data path units. Parallel-prefix
adders (also known as carry-tree adders) are known to have the best performance
in VLSI designs. In this project for simulation we use Modelsim for logical
verification, and further synthesizing it on Xilinx-ISE tool using target technology
and performing placing & routing operation for system verification on targeted
FPGA.
INDUSTRIAL LEARNING (MAJOR PROJECT PROGRAM) [Feb’ 2015]
Project #2 : DESIGN OF EFFICIENT REVERSIBLE MULTIPLY
ACCUMULATE MAC UNIT
ProjectOrganization:
 MTS TECHNOLOGIES Ltd.
ProjectTechnology & Tool Stack :
 Softwares : Xilinx ISEv14.4, ModelSim
 Languages: Verilog, VHDL
 Operating System: Windows 7
Srivalli Siddavatam
Flat no 214, Vibhavari-Towers,opp Gandhi Estate, near Rail-Vihar,
Seri-Lingampally, Hyderabad – 500019
Mobile : 8186055255 Email : ssrivalli1993@gmail.com

2. Srivalli Siddavatam P a g e | 2
ProjectDescription:
 The multiply accumulate unit multiplies the two operands, adds the product to the
previously accumulated result and stores back the new result in the accumulator
all in a single clock cycle, using reversible logic the implementation of digital
circuits known to have the best performance in VLSI designs. In this project for
simulation we use modalsim for logical verification, and further synthesizing it on
Xilinx-ISE tool using target technology and performing placing & routing operation
for system verification on targeted FPGA.
Education TRR ENGINEERING COLLAGE FOR WOMEN – Patancharu,
Hyderabad
Graduation (B.TECH) in Electronicand Communication Engineering–
2015 Passing Out - perceivingwith 65%.
NARAYAN JUNIOR COLLEGE – Kukatpally, Hyderabad
Intermediate - Mathematics and Science Stream (M.P.C) - 2011 Passed
Out withthe aggregate of 65.6%.
RAMAN’S JAVAHAR HIGH SCHOOL – Chandanagar, Hyderabad
SSC (10th) - 2009 Pass-Out withthe aggregate of 63%.
References Available on request
DECLARATION:
I hereby declare thatthe above-mentioned information is correct up to my knowledge
and I bear the responsibility for the correctnessof the above-mentioned particulars.
Place:
Date: (S.Srivalli)