Resume

1. Tejas Kumar Hoizal
tejashoizal0079@gmail.com +91 9676950824
t19145@students.iitmandi.ac.in
EDUCATION
Indian Institute of Technology, Mandi, Master of Technology in VLSI
Aug. 2019 – July. 2021 (expected) CGPA: 8.16 / 10
GATE score EC: 691, Rank: AIR 925 in 2019.
Courses: Analog CMOS LSI Design, Digital MOS LSI circuits, Microelectronics Devices and Modelling
Nano-electronics and nano-microfabrication, Numerical Methods for Engineering Computation
Vardhaman College of Engineering, Hyderabad, Bachelors of Technology in Electronics and Communication Engineering
July. 2011 – July. 2015 CGPA: 7.66 / 10
President of technical club V.I.V.E.C.A from July. 2013 – July. 2014
Organized workshops by collaborating from third party organizations regularly and managing the funds.
WORK EXPERIENCE
Capgemini Technology Services Limited, Bengaluru, India
Associate consultant Oct. 2015 – July. 2018
◦ Managed customer portfolio to facilitate smooth transition for high risk accounts on mainframe-based Credit Card
transactions.
◦ Developed new algorithms to assess the behavior of Accounts and implementing strategies to overcome losses.
◦ Employee of the year for 2018, and star performer awards for three quarters with accompanied monetary benefits.
◦ Identified roadblocks in the automated credit management and customer tracking system and developed solutions to
resolve the mismatches. Client: Australia-New Zealand (ANZ) bank.
ACADEMIC PROJECTS
Ongoing: Speech signal encryption and decryption using Advanced encryption standard(AES).
Guide: Dr. Kunal Ghosh, Assistant Professor, IIT Mandi. Dec. 2019 – Feb. 2020 (expected)
◦ Implementing high secure AES block cipher algorithm using verilog for offline speech communication.
◦ Transmission and recovery of the message is done using MATLAB.
◦ Developing optimized gate level netlist for the algorithm and implementing on FPGA for real time applications
◦ Further study to extend the use of the encryption algorithm for image encryption and decryption.
Perfomance analysis of CMOS full adder for minimum power dissipation and minimum PDP
Guide: Dr. Rahul Shrestha, Assistant Professor, IIT Mandi. Oct. 2019 – Dec. 2019
◦ Recreated the performance of the full adder for difference supply voltages and compared the operating speed and power.
◦ Designed the circuit and layout using Cadence virtuoso tool for minimum power dissipation and verified the the results
in post layout simulation.
CONFERENCES
Attended ”33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems”, The
leela Palace, bengaluru 4th
Jan. 2020 – 8th
Jan. 2020.
OTHER PROJECTS
◦ 80dB, 100MHz Folded cascode two stage Operational amplifier design in UMC130 technology using Cadence virtuoso.
◦ Design and post layout simulation for various flip flops and combinational circuits.
◦ Built Deep learning models to classify images using Convolutional Neural networks in python using Keras and Tensor-
Flow.(Classifying animals, identify digits)
◦ Implemented Projects on Image processing using OpenCV package of Python such as color, face detection, moving object
tracking system and Gesture recognition.
◦ Ranked 30th on the leaderboard in the online hackathon hosted by Analytics Vidhya in research analytics centered around
text analysis.
SKILLS & OTHERS
Programming languages: Verilog, basics of C, python, R, MATLAB
Tools: Cadence, Jupyter, Mainframe, CICS.
Interests: FPGA, Static timing analysis, operational amplifiers, computer vision
Hobbies: Novels, Snooker, Squash, Music
Reference:
Dr. Hitesh Shrimali, Associate Professor, IIT Mandi.
hitesh@iitmandi.ac.in