1. Anuja Bade
Email:bade.anuja123@gmail.com
Mobile: +91-9490848573
CAREER OBJECTIVE
To pursue an eminent career by gaining and applying knowledge and to move
ahead through creativity and consistent performance.
ACADEMIC CREDENTIALS
1. B.Tech in Electronics and Communication Engineering (ECE) from Sasi
Institute of Technology and Engineering (Affiliated to JNTU Kakinada)
with an aggregate of 76.42% in 2015.
2. Intermediate from NRI Sai Junior College (Board of Intermediate) with an
aggregate of 92.4% in 2011.
3. SSC (10
th
) from Navajeevan High School (Board of Secondary Education)
with an aggregate of 88.8% in 2009
EXPERTISE SUMMARY
1. Currently working with Omniphy semiconductors from May 2016 to till
date.
2. Trained at Institute of Silicon Systems in Custom Layout design.
CUSTOM LAYOUT DESIGN SUMMARY
Cadence Tools:
Experience in Custom Layout Designing using Cadence tools.
Virtuoso Layout Editor -Floor Planning and Routing.
Targeted Technology - TSMC 130nm,90nm and GPDK
45nm
Tools Used: Virtuoso Layout Editor, Calibre and PVS.
DIGITAL LAYOUT DESIGNS
Project1: Standard Cells Layout Designing
Cells Designed:INVERTER, NAND, NOR, AND, OR, EX-OR, EX-NOR, MUX and DFF.
Targeted Technology: TSMC 130nm, 90nm.
Role: Drawing the stick diagram from the given spice net list, developing the layout
and verifying DRC and LVS.
2. Anuja Bade
Email:bade.anuja123@gmail.com
Mobile: +91-9490848573
Challenges: Drawing the layout in optimized way using only metal1, maintaining cell
height in terms of metal2 pitches and following half DRC rule for each cell.
ANALOG LAYOUT DESIGNS
Block 1: BGR in TSMC 90nm.
Tools: Calibre for drc and lvs .
Role: : Layout Design for Bandgap Reference.
Challenges: Drawing the layout in an Optimized way, Matching techniques for Differential
pair , CascodeDevices and for BJT’s
Block 2: Operational Amplifier (Op-Amp)
Description: It is used to amplify the difference voltage.
Targeted Technology: GPDK 45nm
Role: Develop Layout from Schematic, Floor Planning, Power Management, Clear DRC
and LVS.
Challenges: Minimum Poly Routing, Matching the Current Mirrors and Differential Pair.
Block 3: Digital to Analog Converter (DAC)
Description: It is used to convert digital to analog.
Targeted Technology: GPDK 45nm
Role: Develop Layout from Schematic, Floor Planning, Power Management, Clear DRC
and LVS.
Challenges: Resistance Matching, Matching the Mismatches to meet the Same
Delay, Placement of Dummies, taking more care on Latch-up Issues, Antenna Effect,
Electro Migration.
SKILLS GAINED
Floor Planning and Power Routing
Debugging DRC and LVS Violations
Matching with respect to PVT
Latch-up
Shielding
Antenna Effect
IR and EM Effects
WPE Effect
STI Effect
