A13 sedra ch 13 cmos digital logic circuits

 Muhammad A M IslamSBE202 Electronic Devices and Circuits 19/21/2020
CMOS Digital Logic Circuits
Chapter 13

INTRODUCTION

Special Characteristics
• Fan-Out
• Power Dissipation
• Propagation Delay
• Noise Margin

Fan-Out
Fan-Out: Min of the two

IOH = 400µA
IIH = 50 µA
IOL = 16 mA
IIL = 1.6 mA
FanOutH = 8
FanOutL = 10
FanOut = 8
Fan-Out

THE DIGITAL LOGIC INVERTERS

Function of the Inverter

The Voltage Transfer Characteristics (VTC)
AmplifierLogic
Inverter
Logic
Inverter

VOL: Output
Low Level
VIL: Max Input
Low Level
VIH: Min Input
High Level
NMH: Noise Margin for High Input
H OH IHNM V V 
L OL ILNM V V 
NML: Noise Margin for Low Input
VOH: Output
High Level
𝑁𝑀 = 𝑀𝑖𝑛 𝑁𝑀𝐿, 𝑁𝑀 𝐻
The Voltage Transfer Characteristics (VTC)
TransitionRegion
Noise Margin

Noise Margin

2
DD
H L
V
NM NM 
The Ideal Voltage Transfer Characteristic

Inverter Implementation
𝑉𝑂𝐿 =
𝑅 𝑜𝑛
𝑅 𝑜𝑛 + 𝑅

Complementary
Switches
Pull-Up (PU) &
Pull-Down (PD)
Switches
𝑉𝑂𝐻 = 𝑉𝐷𝐷𝑉𝑂𝐿 = 0
Signal Swing = Max = 𝑉𝐷𝐷
Noise Margin = Max =
𝑉𝐷𝐷
2
𝑣𝐼 Low𝑣𝐼 High

Current Steering

Example 13.1
Derive expressions for VOH VOL VIL VIH, , and VM
𝑉𝑂𝐻 = 𝑉𝐷𝐷
𝑉𝐼𝐿 =?
𝐼 𝐷 =
1
2
𝑘 𝑛 𝑉𝐼 − 𝑉𝑡
2
𝑣 𝑂 = 𝑉𝐷𝐷 −
1
2
𝑘 𝑛 𝑣𝐼 − 𝑉𝑡
2
𝑅 𝐷
𝜕𝑣 𝑂
𝜕𝑣𝐼
= −1 𝑉𝑥 =
1
𝑘 𝑛 𝑅 𝐷
𝑉𝐼𝐿 = 𝑉𝑥 + 𝑉𝑡
𝑉𝑂𝐻2 = 𝑉𝐷𝐷 −
𝑉𝑥
2
−1 = −
𝑣𝐼 − 𝑉𝑡
𝑉𝑥
Assume λ = 0
𝑉𝑂𝐻2

Example 13.1
𝑉 𝑀 =?
𝑣 𝑂 = 𝑣𝐼 = 𝑉 𝑀
1
2
𝑣𝐼 − 𝑉𝑡
2
𝑉𝑥
𝑣 𝑂 = 𝑣𝐼 − 𝑉𝑡
𝑉 𝑀 = 𝑉𝑡 + 2 𝑉𝐷𝐷 − 𝑉𝑡 𝑉𝑥 + 𝑉𝑥
2
− 𝑉𝑥
𝑉𝑂𝐶 = 2𝑉𝐷𝐷 𝑉𝑥 + 𝑉𝑥
2
− 𝑉𝑥
𝑉𝑂𝐶 =?
𝑉𝐼𝐶 = 𝑉𝑡 + 2𝑉𝐷𝐷 𝑉𝑥 + 𝑉𝑥
2
− 𝑉𝑥

Example 13.1
𝑉𝐼𝐻 =?
𝑉𝐼𝐻 − 𝑉𝑡 = 2𝑉𝑂𝐿2 − 𝑉𝑥
𝑉𝑂𝐿2 = 0.816 𝑉𝐷𝐷 𝑉𝑥
𝐼 𝐷 = 𝑘 𝑛 𝑉𝐼 − 𝑉𝑡 𝑣 𝑂 −
1
2
𝑣 𝑂
2
1
𝑉𝑥
𝑉𝐼 − 𝑉𝑡 𝑣 𝑂 −
1
2
𝑣 𝑂
2
𝜕𝑣 𝑂
𝜕𝑣𝐼
= −1 = −
1
𝑉𝑥
− 𝑉𝐼𝐻 − 𝑉𝑡 +2𝑣 𝑂
𝑉𝐼𝐻 = 𝑉𝑡 + 1.63 𝑉𝐷𝐷 𝑉𝑥 − 𝑉𝑥
𝑉𝑂𝐿2

Example 13.1
𝑉𝑂𝐿 =?
𝑉𝐼 = 𝑉𝐷𝐷
𝑉𝑂𝐿 = 𝑉𝐷𝐷 −
1
𝑉𝑥
𝑉𝐷𝐷 − 𝑉𝑡 𝑉𝑂𝐿 −
1
2
𝑉𝑂𝐿
2
𝑉𝑂𝐿 ≪ 𝑉𝐷𝐷 − 𝑉𝑡
𝑉𝑂𝐿 ≅ 𝑉𝐷𝐷 −
1
𝑉𝑥
𝑉𝐷𝐷 − 𝑉𝑡 𝑉𝑂𝐿
𝑉𝑂𝐿 =
𝑉𝐷𝐷
1 +
𝑉𝐷𝐷 − 𝑉𝑡
𝑉𝑥

2
DDV
R
0Static (On) =
(Off) = 0;
Power Dissipation

2
dyn DDP fCV
Power Dissipation
Dynamic Power Dissipation
0 𝑉𝑉𝐷𝐷 𝑄 = 𝐶𝑉𝐷𝐷
𝐸 = 𝑄𝑉
𝐸 = 𝑄𝑉𝐷𝐷
𝐸 = 𝐶𝑉𝐷𝐷
2
𝑉𝐷𝐷
𝑄
0𝑉

𝑡 𝑃 =
1
2
𝑡 𝑃𝐿𝐻 + 𝑡 𝑃𝐻𝐿
𝑇 𝑚𝑖𝑛 = 𝑡 𝑃𝐿𝐻 + 𝑡 𝑃𝐻𝐿
= 2𝑡 𝑃
Propagation Delay
At 𝑓𝑚𝑎𝑥:

𝑃𝐷𝑃 = 𝑃 𝐷 𝑡 𝑃
Power-Delay and Energy-Delay Products
𝑃𝐷𝑃 = 𝑓𝐶𝑉𝐷𝐷
2
𝑡 𝑃
At max switching frequency, 𝑓𝑚𝑎𝑥 =
1
2𝑡 𝑝
:
𝑃𝐷𝑃 =
1
2
𝐶𝑉𝐷𝐷
2
𝐸𝐷𝑃 =
1
2
𝐶𝑉𝐷𝐷
2
𝑡 𝑃
To optimize a given circuit:
To compare different technologies:
For a given circuit, ↓ 𝑉𝐷𝐷 ↑ 𝑡 𝑃

Silicon Area
3 ways:
1. Device Size (L)
2. Circuits Design
3. Chip Layout
Simpler circuits has 2 effects:
1. ↓ Silicon Area.
2. ↓C → ↓ tp.
3. ↓ I → ↑ tp.

Digital IC Technologies and Logic-Circuit Families

Selection Considerations:
1. logic flexibility (Fan-In and Fan-Out)
2. Speed (𝑡 𝑃)
3. 𝑃𝑑𝑖𝑠𝑠
4. 𝑡 𝑃 × 𝑃𝑑𝑖𝑠𝑠
5. Silicon Area
6. Availability of complex functions,
7. NM.
8. Operating-temperature range
9. $

CMOS: Most Dominant
1. ↓↓ 𝑃𝑑𝑖𝑠𝑠
2. ↑ 𝑧𝑖𝑛
3. ↓ 𝐿

BJT:
1. TTL or T2L: Fading
2. ECL or CML: The fastest.

BiCMOS:
1. Combines the ↑ 𝑔 𝑚 of the BJT, and the many
advantages of CMOS
2. Implements both analog and digital circuits on the
same chip.

GaAs:
1. ↑ 𝜇 → ↑ speed .

ULSI, 100,000s of unconnected
gates. Connections are in factories.
Gate Arrays μPs
Standard ICs Semicustom Custom VLSI ICs
SSI MSI
For Simple Systems Only
Digital Systems
DSPs
>100,000 parts
FPGAs
User Programmable
Styles of Digital-System Design

Design Abstraction and Computer Aids
Standard Cells: similar to subroutines
VHDL: VHSIC Hardware Description Language.
for Digital System Design.

THE CMOS INVERTER

IV
IV
IV
IV
OV
Load
The CMOS Inverter

DD OV V
DD IV V Vt 
IV
IV
IV
IV
The CMOS Inverter
Load

OV
IV
IV
IV
IV
DDV
The CMOS Inverter
Load

Load
DDV
Iv
OV
tV tV
The CMOS Inverter
Load

Active Pull Down
The CMOS Inverter

Active Pull Up
The CMOS Inverter

  21
2
D GS t DS DSI k V V V V
 
    
 
1
I DD DSn
n DD tn
V V r
k V V
    

Active Pull Down
Circuit Operation

 
1
0I DSp
p DD tp
V r
k V V
    

Active Pull Up
Circuit Operation
  21
2
D GS t DS DSI k V V V V
 
    

1. 𝑉𝑂 = 0 & 𝑉𝐷𝐷 𝑀𝑎𝑥 𝑆𝑤𝑖𝑛𝑔
2.0 Static 𝑃𝑑𝑖𝑠𝑠
3.↓ 𝑟 𝐷𝑆𝑝 & 𝑟 𝐷𝑆𝑛 ↓ 𝑉𝑂𝐿 & ↑ 𝑉𝑂𝐻
4.Active Pull up and Pull Down → ↑ Driving Capability
5. 𝑅𝑖𝑛 = ∞ ↑ 𝐹𝑎𝑛 𝑜𝑢𝑡
Circuit Operation
Ideal Characteristics:

   21
2
DN n I tn O O O I tnI k v V v v for v v V
 
      
Qp
    
 
21
2
DP p DD I tp DD O DD O
O I tp
I k V v V V v V v
for v v V
 
       
 
   
21
2
DN n I tn O I tnI k v V for v v V   
   
21
2
DP p DD I tp O I tpI k V v V for v v V    
Voltage Transfer Characteristic

p n
n p
W
W



Matching

𝑉 𝑀
VOH
VOL

   
2
21 1
2 2
I tn O O DD I tpv V v v V v V    
 
1
5 2
8
IH DD tV V V 
   O O
I tn O O DD I tp
I I
dv dv
v V v v V v V
dv dv
      
VIH: Qn Tri; Qp Sat
2
DD
OL IH
V
v V 
, , & 1,O
I IH O OL
I
dv
v V v V
dv
   
Dn DpI I
 
1
2
8
OL DD tV V V 

𝑉 𝑀
 
1
5 2
8
IH DD tV V V 
From the Symmetry
IL DD IHV V V Q
 
1
3 2
8
IL DD tV V V  
 
1
7 2
8
OH DD tV V V  
OH DD OLV V V Q
VIH: Qn Tri; Qp Sat
 
1
2
8
DD DD tV V V  

Noise Margin
H OH IHNM V V 
L IL OLNM V V 
 
1
2
4
H L DD tNM NM NM V V   

Noise Margin
 
1
DD tp tn
M
r V V V
V
r
 


p
n
k
r
k

The Situation when QN & QP Are Not Matched
↓ 𝑟 ↓ 𝑆𝑖𝑙𝑖𝑐𝑜𝑛 𝐴𝑟𝑒𝑎 & 𝑠𝑚𝑎𝑙𝑙 ∆𝑉 𝑀

DYNAMIC OPERATION OF THE CMOS
INVERTER

Dynamic Operation of the CMOS Inverter
Determining the Propagation Delay
𝛼 𝑛 =
2
7
4
−
3𝑉𝑡𝑛
𝑉𝐷𝐷
+
𝑉𝑡𝑛
𝑉𝐷𝐷
2
𝑡 𝑃𝐷 =
1
2
𝑡 𝑃𝐻𝐿 + 𝑡 𝑃𝐿𝐻
𝑡 𝑃𝐻𝐿 =
𝛼 𝑛 𝐶
𝐾 𝑛 𝑉𝐷𝐷
𝑡 𝑃𝐿𝐻 =
𝛼 𝑝 𝐶
𝐾 𝑝 𝑉𝐷𝐷
𝛼 𝑝 =
2
7
4
−
3 𝑉𝑡𝑝
𝑉𝐷𝐷
+
𝑉𝑡𝑛
𝑉𝐷𝐷
2
1 2

↓ tP:
1. ↓C ← ↓ ( L & W & Layout)
2. ↑ 𝑘 ← (↑ W , ↓ L & ↑ µ )
3. ↑VDD !! NO:
i. Determined by the process technology ↓ .
ii. ↑ 𝑃𝑑𝑖𝑠𝑠.
P
DD
C
t
kV

 n pk k k Matched Qs: n p   

 Muhammad A M Islam 659/21/2020SBE202 Electronic Devices and Circuits
An Alternative Approach
𝑉𝐷𝐷
2
= 𝑉𝐷𝐷 𝑒
−
𝑡 𝑃𝐻𝐿
𝑅 𝑁 𝐶
𝑡 𝑃𝐻𝐿 = 𝑅 𝑁 𝐶 𝑙𝑛2 𝑅 𝑁 =
12.5
𝑊
𝐿 𝑛
kΩ

 Muhammad A M Islam 669/21/2020SBE202 Electronic Devices and Circuits
An Alternative Approach
𝑡 𝑃𝐿𝐻 = 𝑅 𝑃 𝐶 𝑙𝑛2 𝑅 𝑃 =
30
𝑊
𝐿 𝑝
kΩ

 Muhammad A M IslamMTI BIO 313 Electron ic Vision 699/21/2020
DDV V 
Propagation Delay AC: Parallel
outC
1 1 2 3 4db db g g wC C C C C C    
2 DDV V 
1 2 1 2 3 42 2out gd gd db db g g wC C C C C C C C      
Q
C
V

Parallel
Repalce Cgd1 & Cgd2 with a Ce
bet’ D & Ground, that draws
the same Q.
 1 22 dd gd gd dd eQ V C C V C  
 1 22e gd gdC C C 

Inverter Sizing
Selecting appropriate
𝑊
𝐿
ratios
1. Min L.
2.
𝑊
𝐿 𝑛
=?
i. 1 1.5 for min silicon area.
ii. ↑
𝑊
𝐿 𝑛
↓ 𝑡 𝑃
3.
𝑊
𝐿 𝑝
=?
i.
𝑊
𝐿 𝑝
=
𝑘 𝑛
′
𝑘 𝑝
′
𝑊
𝐿
𝑛
𝑀𝑎𝑡𝑐ℎ𝑖𝑛𝑔
𝑜𝑝𝑡𝑖𝑚𝑎𝑙 𝑡 𝑃𝐿𝐻 & 𝑁𝑀 & ↑ 𝐴𝑟𝑒𝑎 &𝐶 .
ii. Compromise: 2
𝑊
𝐿 𝑛

Power Dissipation
Static Power Dissipation = 0
Current Flow and Power Dissipation
2
dyn DDP fCVDynamic Power Dissipation
↑ #𝑇𝑟𝑠 ↑ 𝐶
↓ 𝑉𝐷𝐷 ↓ 𝑃𝑑𝑦𝑛
Switching Power Dissipation ≪ 𝑃𝑑𝑦𝑛
𝐼 𝑃𝑒𝑎𝑘 =
1
2
𝑘
𝑉𝐷𝐷
2
− 𝑉𝑡
2
For matched Qs

CMOS LOGIC-GATE CIRCUITS

O Iv v
Basic Structure
PMOS
Iv
NMOS
Iv

PMOS
NMOS
 , ,y f A B C
Y in S.O.P. Form
Basic Structure
 , ,y f A B C , ,y g A B C

Pull-down Networks

Pull-Up Networks

Alternative Circuit Symbols for MOSFETs

Active Low
Alternative Circuit Symbols for MOSFETs

Y A B 
Y A B A B   
Y A B 
The Two-Input CMOS NOR Gate

Y A B A B   
Y A B 
Y A B 
The Two-Input CMOS NAND Gate

 Y A B CD 
 Y A B CD 
  Y A B CD  
Y A B CD  
 Y A B C D   
A Complex Gate

Duality
PUN ⟺ PDN
1. PMOS ↔ NMOS
2. Parallel ↔ Serial

The Exclusive-OR Function
Y AB AB 
Y AB AB 
   Y A B A B  g

Transistor Sizing
?
W
L

n & p: Conductance or Resistance?
Imin ≥ I basic_inverter
𝑛 ≡
𝑊
𝐿 𝑛
𝑝 ≡
𝑊
𝐿 𝑝
𝐼 𝐷 = 𝑘 𝑛
′
𝑊
𝐿
𝑉𝐼 − 𝑉𝑡 𝑣 𝑂 −
1
2
𝑣 𝑂
2 𝐼 𝐷 𝛼
𝑊
𝐿
Conductance

CMOS Inverter Circuit Structure
 
1
DSN
n DD t
r
k V V


 
1
DSP
p DD t
r
k V V


 '
1
n DD t
n
W
k V V
L

   
 
DSP DSNr r
 '
1
n DD tk n V V


1
DSNr
n

1
DSPr
p


Transistor Sizing
Imin ≥ I basic_inverter
1
DSNr
n

1
DSPr
p

nY n pY p
𝑛 & 𝑝:

Transistor Sizing

Example 13.7
?
W
L

Basic inverter:
n = 1.5
p = 5
L=0.25 µm
𝑊𝑛 = 0.375 µm
𝑊𝑝 = 1.25 µm

2-input Multiplexer CMOS Circuit

Fan-In
# # Pinputs Transistors C t   
2 transistors per input
Practical limit:
Ex: NAND = 4 inputs
To ↑ # inputs  Multisage
Effects of Fan-In and Fan-Out on Propagation Delay

Fan-Out
# Poutputs C t  
Effects of Fan-In and Fan-Out on Propagation Delay

A13 sedra ch 13 cmos digital logic circuits

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