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- 1. Computer Organization UNIT 1 Prepared By Prof. Rakesh Roshan [email_address] n Prof. RAKESH ROSHAN 09971640291
- 2. REGISTER TRANSFER AND MICROOPERATIONS • Register Transfer Language • Register Transfer • Bus and Memory Transfers • Arithmetic Microoperations • Logic Microoperations • Shift Microoperations • Arithmetic Logic Shift Unit Prof. RAKESH ROSHAN 09971640291
- 3. SIMPLE DIGITAL SYSTEMS <ul><li>Combinational and sequential circuits </li></ul><ul><li>can be used to create simple digital systems. </li></ul><ul><li>These are the low-level building blocks of a digital computer. </li></ul><ul><li>Simple digital systems are frequently characterized in terms of </li></ul><ul><ul><li>the registers they contain, and </li></ul></ul><ul><ul><li>the operations that they perform. </li></ul></ul><ul><li>Typically, </li></ul><ul><ul><li>What operations are performed on the data in the registers </li></ul></ul><ul><ul><li>What information is passed between registers </li></ul></ul>Prof. RAKESH ROSHAN 09971640291
- 4. MICROOPERATIONS (1) <ul><li>The operations on the data in registers are called microoperations. </li></ul><ul><li>The functions built into registers are examples of microoperations </li></ul><ul><ul><li>Shift </li></ul></ul><ul><ul><li>Load </li></ul></ul><ul><ul><li>Clear </li></ul></ul><ul><ul><li>Increment </li></ul></ul><ul><ul><li>… </li></ul></ul>Register Transfer Language Prof. RAKESH ROSHAN 09971640291
- 5. MICROOPERATION (2) An elementary operation performed (during one clock pulse), on the information stored in one or more registers R f(R, R) f: shift, load, clear, increment, add, subtract, complement, and, or, xor, … 1 clock cycle Register Transfer Language Prof. RAKESH ROSHAN 09971640291 ALU (f) Registers (R)
- 6. ORGANIZATION OF A DIGITAL SYSTEM - Set of registers and their functions - Microoperations set Set of allowable microoperations provided by the organization of the computer - Control signals that initiate the sequence of microoperations (to perform the functions) <ul><li>Definition of the (internal) organization of a computer </li></ul>Register Transfer Language Prof. RAKESH ROSHAN 09971640291
- 7. REGISTER TRANSFER LEVEL <ul><li>Viewing a computer, or any digital system, in this way is called the register transfer level </li></ul><ul><li>This is because we’re focusing on </li></ul><ul><ul><li>The system’s registers </li></ul></ul><ul><ul><li>The data transformations in them, and </li></ul></ul><ul><ul><li>The data transfers between them. </li></ul></ul>Register Transfer Language Prof. RAKESH ROSHAN 09971640291
- 8. REGISTER TRANSFER LANGUAGE <ul><li>Rather than specifying a digital system in words, a specific notation is used, register transfer language </li></ul><ul><li>For any function of the computer, the register transfer language can be used to describe the (sequence of) microoperations </li></ul><ul><li>Register transfer language </li></ul><ul><ul><li>A symbolic language </li></ul></ul><ul><ul><li>A convenient tool for describing the internal organization of digital computers </li></ul></ul><ul><ul><li>Can also be used to facilitate the design process of digital systems. </li></ul></ul>Register Transfer Language Prof. RAKESH ROSHAN 09971640291
- 9. DESIGNATION OF REGISTERS <ul><li>Registers are designated by capital letters, sometimes followed by numbers (e.g., A, R13, IR) </li></ul><ul><li>Often the names indicate function: </li></ul><ul><ul><li>MAR - memory address register </li></ul></ul><ul><ul><li>PC - program counter </li></ul></ul><ul><ul><li>IR - instruction register </li></ul></ul><ul><li>Registers and their contents can be viewed and represented in various ways </li></ul><ul><ul><li>A register can be viewed as a single entity: </li></ul></ul><ul><ul><li>Registers may also be represented showing the bits of data they contain </li></ul></ul>Register Transfer Language MAR Prof. RAKESH ROSHAN 09971640291
- 10. DESIGNATION OF REGISTERS Register Transfer Language R1 Register Numbering of bits Showing individual bits Subfields PC(H) PC(L) 15 8 7 0 - a register - portion of a register - a bit of a register <ul><li>Common ways of drawing the block diagram of a register </li></ul>7 6 5 4 3 2 1 0 R2 15 0 <ul><li>Designation of a register </li></ul>Prof. RAKESH ROSHAN 09971640291
- 11. REGISTER TRANSFER <ul><li>Copying the contents of one register to another is a register transfer </li></ul><ul><li>A register transfer is indicated as </li></ul><ul><ul><li>R2 R1 </li></ul></ul><ul><ul><li>In this case the contents of register R2 are copied (loaded) into register R1 </li></ul></ul><ul><ul><li>A simultaneous transfer of all bits from the source R1 to the destination register R2, during one clock pulse </li></ul></ul><ul><ul><li>Note that this is a non-destructive; i.e. the contents of R1 are not altered by copying (loading) them to R2 </li></ul></ul>Register Transfer Prof. RAKESH ROSHAN 09971640291
- 12. REGISTER TRANSFER <ul><li>A register transfer such as </li></ul><ul><ul><li>R3 R5 </li></ul></ul><ul><ul><li>Implies that the digital system has </li></ul></ul><ul><ul><li>the data lines from the source register (R5) to the destination register (R3) </li></ul></ul><ul><ul><li>Parallel load in the destination register (R3) </li></ul></ul><ul><ul><li>Control lines to perform the action </li></ul></ul>Register Transfer Prof. RAKESH ROSHAN 09971640291
- 13. CONTROL FUNCTIONS <ul><li>Often actions need to only occur if a certain condition is true </li></ul><ul><li>This is similar to an “if” statement in a programming language </li></ul><ul><li>In digital systems, this is often done via a control signal , called a control function </li></ul><ul><ul><li>If the signal is 1, the action takes place </li></ul></ul><ul><li>This is represented as: </li></ul><ul><ul><li>P: R2 R1 </li></ul></ul><ul><ul><li>Which means “if P = 1, then load the contents of register R1 into register R2”, i.e., if (P = 1) then (R2 R1) </li></ul></ul>Register Transfer Prof. RAKESH ROSHAN 09971640291
- 14. HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS Implementation of controlled transfer P: R2 R1 Block diagram Timing diagram Clock Register Transfer Transfer occurs here R2 R1 Control Circuit Load P n Clock Load t t+1 The block diagram that depicts the transfer from R1 to R2. The n outputs of register R1 are connected to the n inputs of register R2. The letter n will be used to indicate any number of bits for the register. It will be replaced by an actual number when the length Of the register is known. Register R2 has load input that is activated by the control variable P. In timing diagram , P is activated in the control section by the rising edge of a clock pulse at time t. The next positive transition of the clock at time t+1 finds the load active and the data inputs of R2 are then loaded into the register in parallel. P may go back to 0 at Time t+1; otherwise, the transfer will occur with every clock pulse transition while P remains active. Prof. RAKESH ROSHAN 09971640291
- 15. SIMULTANEOUS OPERATIONS <ul><li>If two or more operations are to occur simultaneously, they are separated with commas </li></ul><ul><ul><li>P: R3 R5 , MAR IR </li></ul></ul><ul><li>Here, if the control function P = 1, load the contents of R5 into R3, and at the same time (clock), load the contents of register IR into register MAR </li></ul>Register Transfer Prof. RAKESH ROSHAN 09971640291
- 16. BASIC SYMBOLS FOR REGISTER TRANSFERS Capital letters Denotes a register MAR, R2 & numerals Parentheses () Denotes a part of a register R2(0-7), R2(L) Arrow Denotes transfer of information R2 R1 Colon : Denotes termination of control function P: Comma , Separates two micro-operations A B, B A Symbols Description Examples Register Transfer Prof. RAKESH ROSHAN 09971640291
- 17. Bus and Memory Transfer <ul><li>Bus is a path(of a group of wires) over which information is transferred, from any of several sources to any of several destinations. </li></ul><ul><li>A digital computer has many registers, and paths must be provided to transfer information from one register to another. The number of wires will be excessive if separate lines are used between each register and all other registers in the system. A more efficient scheme for transferring information between registers in a multiple-register configuration is a common bus system. </li></ul><ul><li>A bus structure consists of a set of common lines, one for each bit of a register, through which binary information is transferred one at a time. Control signals determine which register is selected by the bus during each particular register transfer. </li></ul>Register Transfer Prof. RAKESH ROSHAN 09971640291
- 18. Bus System for four registers From a register to bus: BUS R Bus and Memory Transfers We can construct the common bus system is with multiplexers. The multiplexers select the source Register whose binary information is then placed on the bus. Prof. RAKESH ROSHAN 09971640291 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 Register A Register B Register C Register D B C D 1 1 1 4 x1 MUX B C D 2 2 2 4 x1 MUX B C D 3 3 3 4 x1 MUX B C D 4 4 4 4 x1 MUX 4-line bus x y select 0 0 0 0 Register A Register B Register C Register D Bus lines x y Register Selected 0 0 A 0 1 B 1 0 C 1 1 D
- 19. TRANSFER FROM BUS TO A DESTINATION REGISTER Three-State Bus Buffers Bus line with three-state buffers Output Y=A if C=1 High-impedence if C=0 Normal input A Control input C Select Enable 0 1 2 3 S0 S1 A0 B0 C0 D0 Bus line for bit 0 Bus and Memory Transfers A bus system can be constructed with three-state gated instead of multiplexers. A three-state gate Is a digital circuit that exhibits three states. Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate. The third state is a high-impedance state. The high-impedance state Behaves like an open circuit, which means that the output is disconnected and does not have A logic significance. Three-state gates may perform any conventional logic, such as AND and NAND. However, the one most commonly used in the design of a bus system is the buffer gate. In the above diagram, The outputs of four buffers are connected together to form a single bus line . The control inputs to the buffers determine which of the four normal inputs will communicate With the bus line. No more than one buffer may be in the active state at any given time. The Connected buffers must be controlled so that only one three-state buffer has access to the bus line while all other buffers are maintained in a high impedance state. Prof. RAKESH ROSHAN 09971640291
- 20. BUS TRANSFER IN RTL <ul><li>Depending on whether the bus is to be mentioned explicitly or not, register transfer can be indicated as either </li></ul><ul><li>or </li></ul><ul><li>In the former case the bus is implicit, but in the latter, it is explicitly indicated </li></ul>Bus and Memory Transfers R2 R1 BUS R1, R2 BUS Prof. RAKESH ROSHAN 09971640291
- 21. MEMORY (RAM) <ul><li>Memory (RAM) can be thought as a sequential circuits containing some number of registers </li></ul><ul><li>These registers hold the words of memory </li></ul><ul><li>Each of the r registers is indicated by an address </li></ul><ul><li>These addresses range from 0 to r-1 </li></ul><ul><li>Each register (word) can hold n bits of data </li></ul><ul><li>Assume the RAM contains r = 2 k words. It needs the following </li></ul><ul><ul><li>n data input lines </li></ul></ul><ul><ul><li>n data output lines </li></ul></ul><ul><ul><li>k address lines </li></ul></ul><ul><ul><li>A Read control line </li></ul></ul><ul><ul><li>A Write control line </li></ul></ul>Bus and Memory Transfers Prof. RAKESH ROSHAN 09971640291 data input lines data output lines n n k address lines Read Write RAM unit
- 22. MEMORY TRANSFER <ul><li>Collectively, the memory is viewed at the register level as a device, M. </li></ul><ul><li>Since it contains multiple locations, we must specify which address in memory we will be using </li></ul><ul><li>This is done by indexing memory references </li></ul><ul><li>Memory is usually accessed in computer systems by putting the desired address in a special register, the Memory Address Register ( MAR , or AR ) </li></ul><ul><li>When memory is accessed, the contents of the MAR get sent to the memory unit’s address lines </li></ul>Bus and Memory Transfers M Prof. RAKESH ROSHAN 09971640291 AR Memory unit Read Write Data in Data out
- 23. MEMORY READ <ul><li>To read a value from a location in memory and load it into a register, the register transfer language notation looks like this: </li></ul><ul><li>This causes the following to occur </li></ul><ul><ul><li>The contents of the MAR get sent to the memory address lines </li></ul></ul><ul><ul><li>A Read (= 1) gets sent to the memory unit </li></ul></ul><ul><ul><li>The contents of the specified address are put on the memory’s output data lines </li></ul></ul><ul><ul><li>These get sent over the bus to be loaded into register R1 </li></ul></ul>Bus and Memory Transfers R1 M[MAR] Prof. RAKESH ROSHAN 09971640291
- 24. MEMORY WRITE <ul><li>To write a value from a register to a location in memory looks like this in register transfer language: </li></ul><ul><li>This causes the following to occur </li></ul><ul><ul><li>The contents of the MAR get sent to the memory address lines </li></ul></ul><ul><ul><li>A Write (= 1) gets sent to the memory unit </li></ul></ul><ul><ul><li>The values in register R1 get sent over the bus to the data input lines of the memory </li></ul></ul><ul><ul><li>The values get loaded into the specified address in the memory </li></ul></ul>Bus and Memory Transfers M[MAR] R1 Prof. RAKESH ROSHAN 09971640291
- 25. SUMMARY OF R. TRANSFER MICROOPERATIONS Bus and Memory Transfers A B Transfer content of reg. B into reg. A AR DR(AD) Transfer content of AD portion of reg. DR into reg. AR A constant Transfer a binary constant into reg. A ABUS R1, Transfer content of R1 into bus A and, at the same time, R2 ABUS transfer content of bus A into R2 AR Address register DR Data register M[R] Memory word specified by reg. R M Equivalent to M[AR] DR M Memory read operation: transfers content of memory word specified by AR into DR M DR Memory write operation: transfers content of DR into memory word specified by AR Prof. RAKESH ROSHAN 09971640291
- 26. MICROOPERATIONS <ul><li>Computer system microoperations are of four types: </li></ul>- Register transfer microoperations - Arithmetic microoperations - Logic microoperations - Shift microoperations Arithmetic Microoperations Prof. RAKESH ROSHAN 09971640291
- 27. ARITHMETIC MICROOPERATIONS <ul><li>The basic arithmetic microoperations are </li></ul><ul><ul><li>Addition </li></ul></ul><ul><ul><li>Subtraction </li></ul></ul><ul><ul><li>Increment </li></ul></ul><ul><ul><li>Decrement </li></ul></ul><ul><li>The additional arithmetic microoperations are </li></ul><ul><ul><li>Add with carry </li></ul></ul><ul><ul><li>Subtract with borrow </li></ul></ul><ul><ul><li>Transfer/Load </li></ul></ul><ul><ul><li>etc. … </li></ul></ul>Summary of Typical Arithmetic Micro-Operations Arithmetic Microoperations <ul><ul><li>R3 R1 + R2 Contents of R1 plus R2 transferred to R3 </li></ul></ul><ul><ul><li>R3 R1 - R2 Contents of R1 minus R2 transferred to R3 </li></ul></ul><ul><ul><li>R2 R2’ Complement the contents of R2 </li></ul></ul><ul><ul><li>R2 R2’+ 1 2's complement the contents of R2 (negate) </li></ul></ul><ul><ul><li>R3 R1 + R2’+ 1 subtraction </li></ul></ul><ul><ul><li>R1 R1 + 1 Increment </li></ul></ul><ul><ul><li>R1 R1 - 1 Decrement </li></ul></ul>Prof. RAKESH ROSHAN 09971640291
- 28. BINARY ADDER / SUBTRACTOR / INCREMENTER Binary Adder-Subtractor Binary Adder Arithmetic Microoperations The addition and subtraction operations can be combined into one common circuit by including An exclusive-OR gate with full adder. In 4-bit adder-subtractor circuit, the mode input M controls The operation. When M=0 the circuit is an adder and when M=1 the circuit becomes a subtractor. Each exclusive-OR gate receive input M and one of the inputs of B. When M=0, we have B 0=B. The full adders receives the value of B, input carry is 0, and the circuit performs A plus B. When M=1 we have B 1=B’ and C0 = 1. The B inputs are all complemented and a 1 is added through The input carry. The circuit performs the operation A plus the 2’s complement of B. Prof. RAKESH ROSHAN 09971640291
- 29. Binary Incrementer <ul><li>The above diagram represents the 4-bit Binary incrementer using Half-Adder. One of the inputs to the least significant half-adder is connected to logic-1 and the other input is connected to the least significant bit of the number to be incremented. The output carry from one half-adder is connected to one of the inputs of the next-higher-order half-adder. The circuit receives the four bits from A0 through A3 , adds one to it and generates the incremented output in S0 through S3. The output carry C4 will be 1 only after incrementing binary 1111. This also causes outputs S0 through S3 to go to 0. </li></ul>Prof. RAKESH ROSHAN 09971640291
- 30. ARITHMETIC CIRCUIT S1 S0 Cin Y Output Microoperation 0 0 0 B D = A + B Add 0 0 1 B D = A + B + 1 Add with carry 0 1 0 B’ D = A + B’ Subtract with borrow 0 1 1 B’ D = A + B’+ 1 Subtract 1 0 0 0 D = A Transfer A 1 0 1 0 D = A + 1 Increment A 1 1 0 1 D = A - 1 Decrement A 1 1 1 1 D = A Transfer A Arithmetic Microoperations Prof. RAKESH ROSHAN 09971640291 S1 S0 0 1 2 3 4x1 MUX X0 Y0 C0 C1 D0 FA S1 S0 0 1 2 3 4x1 MUX X1 Y1 C1 C2 D1 FA S1 S0 0 1 2 3 4x1 MUX X2 Y2 C2 C3 D2 FA S1 S0 0 1 2 3 4x1 MUX X3 Y3 C3 C4 D3 FA Cout A0 B0 A1 B1 A2 B2 A3 B3 0 1 S0 S1 Cin
- 31. Arithmetic Circuit Contd….. <ul><li>Addition : When S 1 S 0 =00, the value of B is applied to the Y inputs of the adder. If C in =0, the output D=A+B. If C in =1, output D=A+B+1. Both perform the add micro operation with or without adding the input carry. </li></ul><ul><li>Subtraction : When S 1 S 0 =01, the complement of B is applied to the Y inputs of the adder. If C in =1 , then D=A+B’+1. This produces A plus the 2’s complement of B , which is equivalent to a subtraction of A-B. When C in =0 , then D=A+B’. This is equivalent to a subtract with borrow , that is , A-B-1. </li></ul><ul><li>Increment : When S 1 S 0 =10, the inputs from B are neglected, and instead, all 0’s are inserted into the Y inputs. The output becomes D=A+0+C in .This gives D=A when C in =0 and D=A+1 when C in =1. In the first case we have a direct transfer from input A to output D. In the second case, the value of A is incremented by 1. </li></ul><ul><li>Decrement: When S 1 S 0 =11, all 1’s are inserted into the Y inputs of the adder to produce the decremented operation D=A-1 when C in =0. This is because a number with all 1’s is equal to the 2’s complement of 1 ( the 2’s complement of binary 0001 is 1111). Adding a number A to the 2’s complement of 1 produces F=A+2’s complement of 1=A-1.When C in =1, then D=A-1+1=A, which causes a direct transfer from input A to output D. </li></ul>Prof. RAKESH ROSHAN 09971640291
- 32. LOGIC MICROOPERATIONS <ul><li>Specify binary operations on the strings of bits in registers </li></ul><ul><ul><li>Logic micro operations are bit-wise operations, i.e., they work on the individual bits of data </li></ul></ul><ul><ul><li>useful for bit manipulations on binary data </li></ul></ul><ul><ul><li>useful for making logical decisions based on the bit value </li></ul></ul><ul><li>There are, in principle, 16 different logic functions that can be defined over two binary input variables </li></ul><ul><li>However, most systems only implement four of these </li></ul><ul><ul><li>AND ( ), OR ( ), XOR ( ), Complement/NOT </li></ul></ul><ul><li>The others can be created from combination of these </li></ul><ul><li>Example: the exclusive-OR microoperation with the contents of two registers R1 and R2 is symbolized by the statement </li></ul><ul><li>P: R1 R1 R2 </li></ul><ul><li>It specifies that a logic microoperation to be executed on the individual bits of the registers provided that the control variable P=1. </li></ul>Logic Microoperations Prof. RAKESH ROSHAN 09971640291
- 33. LIST OF LOGIC MICROOPERATIONS <ul><li>List of Logic Microoperations </li></ul><ul><li>- 16 different logic operations with 2 binary vars. </li></ul><ul><li>- n binary vars -> functions </li></ul>2 2 n <ul><li>Truth tables for 16 functions of 2 variables and the </li></ul><ul><li>corresponding 16 logic micro-operations </li></ul>Boolean Function Micro- Operations Name x 0 0 1 1 y 0 1 0 1 Logic Microoperations <ul><ul><li>0 0 0 0 F0 = 0 F 0 Clear </li></ul></ul><ul><ul><li>0 0 0 1 F1 = xy F A B AND </li></ul></ul><ul><ul><li>0 0 1 0 F2 = xy' F A B’ </li></ul></ul><ul><ul><li>0 0 1 1 F3 = x F A Transfer A </li></ul></ul><ul><ul><li>0 1 0 0 F4 = x'y F A’ B </li></ul></ul><ul><ul><li>0 1 0 1 F5 = y F B Transfer B </li></ul></ul><ul><ul><li>0 1 1 0 F6 = x y F A B Exclusive-OR </li></ul></ul><ul><ul><li>0 1 1 1 F7 = x + y F A B OR </li></ul></ul><ul><ul><li>1 0 0 0 F8 = (x + y)' F A B)’ NOR </li></ul></ul><ul><ul><li>1 0 0 1 F9 = (x y)' F (A B)’ Exclusive-NOR </li></ul></ul><ul><ul><li>1 0 1 0 F10 = y' F B’ Complement B </li></ul></ul><ul><ul><li>1 0 1 1 F11 = x + y' F A B </li></ul></ul><ul><ul><li>1 1 0 0 F12 = x' F A’ Complement A </li></ul></ul><ul><ul><li>1 1 0 1 F13 = x' + y F A’ B </li></ul></ul><ul><ul><li>1 1 1 0 F14 = (xy)' F (A B)’ NAND </li></ul></ul><ul><ul><li>1 1 1 1 F15 = 1 F all 1's Set to all 1's </li></ul></ul>Prof. RAKESH ROSHAN 09971640291
- 34. HARDWARE IMPLEMENTATION OF LOGIC MICROOPERATIONS 0 0 F = A B AND 0 1 F = A B OR 1 0 F = A B XOR 1 1 F = A’ Complement S 1 S 0 Output -operation Function table Logic Microoperations Prof. RAKESH ROSHAN 09971640291 B A S S F 1 0 i i i 0 1 2 3 4 X 1 MUX Select
- 35. APPLICATIONS OF LOGIC MICROOPERATIONS <ul><li>Logic microoperations can be used to manipulate individual bits or a portions of a word in a register </li></ul><ul><li>Consider the data in a register A. In another register, B, is bit data that will be used to modify the contents of A </li></ul><ul><ul><li>Selective-set A A + B </li></ul></ul><ul><ul><li>Selective-complement A A B </li></ul></ul><ul><ul><li>Selective-clear A A • B’ </li></ul></ul><ul><ul><li>Mask (Delete) A A • B </li></ul></ul><ul><ul><li>Clear A A B </li></ul></ul><ul><ul><li>Insert A (A • B) + C </li></ul></ul><ul><ul><li>Compare A A B </li></ul></ul>Logic Microoperations Prof. RAKESH ROSHAN 09971640291
- 36. SELECTIVE SET <ul><li>In a selective set operation, the bit pattern in B is used to set certain bits in A </li></ul><ul><li>1 1 0 0 A t </li></ul><ul><li>1 0 1 0 B </li></ul><ul><li>1 1 1 0 A t+1 (A A + B) </li></ul><ul><li>If a bit in B is set to 1, that same position in A gets set to 1, otherwise that bit in A keeps its previous value </li></ul>Logic Microoperations Prof. RAKESH ROSHAN 09971640291
- 37. SELECTIVE COMPLEMENT <ul><li>In a selective complement operation, the bit pattern in B is used to complement certain bits in A </li></ul><ul><li>1 1 0 0 A t </li></ul><ul><li>1 0 1 0 B </li></ul><ul><li>0 1 1 0 A t+1 (A A B) </li></ul><ul><li>If a bit in B is set to 1, that same position in A gets complemented from its original value, otherwise it is unchanged </li></ul>Logic Microoperations Prof. RAKESH ROSHAN 09971640291
- 38. SELECTIVE CLEAR <ul><li>In a selective clear operation, the bit pattern in B is used to clear certain bits in A </li></ul><ul><li>1 1 0 0 A t </li></ul><ul><li>1 0 1 0 B </li></ul><ul><li>0 1 0 0 A t+1 (A A B’) </li></ul><ul><li>If a bit in B is set to 1, that same position in A gets set to 0, otherwise it is unchanged </li></ul>Logic Microoperations Prof. RAKESH ROSHAN 09971640291
- 39. MASK OPERATION <ul><li>In a mask operation, the bit pattern in B is used to clear certain bits in A </li></ul><ul><li>1 1 0 0 A t </li></ul><ul><li>1 0 1 0 B </li></ul><ul><li>1 0 0 0 A t+1 (A A B) </li></ul><ul><li>If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is unchanged </li></ul>Logic Microoperations Prof. RAKESH ROSHAN 09971640291
- 40. CLEAR OPERATION <ul><li>In a clear operation, if the bits in the same position in A and B are the same, they are cleared in A, otherwise they are set in A </li></ul><ul><li>1 0 1 0 A t </li></ul><ul><li>1 0 1 0 B </li></ul><ul><li>0 0 0 0 A t+1 (A A B) </li></ul>Logic Microoperations Prof. RAKESH ROSHAN 09971640291
- 41. INSERT OPERATION <ul><li>An insert operation is used to introduce a specific bit pattern into A register, leaving the other bit positions unchanged </li></ul><ul><li>This is done as </li></ul><ul><ul><li>A mask operation to clear the desired bit positions, followed by </li></ul></ul><ul><ul><li>An OR operation to introduce the new bits into the desired positions </li></ul></ul><ul><ul><li>Example </li></ul></ul><ul><ul><ul><li>Suppose you wanted to introduce 1010 into the low order four bits of A: 1101 1000 1011 0001 A (Original) 1101 1000 1011 1010 A (Desired) </li></ul></ul></ul><ul><ul><ul><li>1101 1000 1011 0001 A (Original) </li></ul></ul></ul><ul><ul><ul><li>1111 1111 1111 0000 Mask </li></ul></ul></ul><ul><ul><ul><li>1101 1000 1011 0000 A (Intermediate) </li></ul></ul></ul><ul><ul><ul><li>0000 0000 0000 1010 Added bits </li></ul></ul></ul><ul><ul><ul><li>1101 1000 1011 1010 A (Desired) </li></ul></ul></ul>Logic Microoperations Prof. RAKESH ROSHAN 09971640291
- 42. SHIFT MICROOPERATIONS <ul><li>There are three types of shifts </li></ul><ul><ul><li>Logical shift </li></ul></ul><ul><ul><li>Circular shift </li></ul></ul><ul><ul><li>Arithmetic shift </li></ul></ul>Shift Microoperations <ul><li>A right shift operation </li></ul><ul><li>A left shift operation </li></ul>Shift micro operations are used for serial transfer of data. They are also used in conjunction with arithmetic, Logic and other data-processing operations. The contents of a register can be shifted to the left or the right. At the same time that the bits are shifted , the first flip-flop receives its binary information from the serial Input. During a shift-left operation the serial input transfers a bit into the rightmost position . During a shift- Right operation the serial inputs transfers a bit into the leftmost position. The information transferred through the serial input determines the type of shift. Prof. RAKESH ROSHAN 09971640291 Serial input Serial input
- 43. LOGICAL SHIFT <ul><li>In a logical shift the serial input to the shift is a 0. </li></ul><ul><li>A right logical shift operation: </li></ul><ul><li>A left logical shift operation: </li></ul><ul><li>In a Register Transfer Language, the following notation is used </li></ul><ul><ul><li>shl for a logical shift left </li></ul></ul><ul><ul><li>shr for a logical shift right </li></ul></ul><ul><ul><li>Examples: </li></ul></ul><ul><ul><ul><li>R2 shr R2 </li></ul></ul></ul><ul><ul><ul><li>R3 shl R3 </li></ul></ul></ul>Shift Microoperations Prof. RAKESH ROSHAN 09971640291 0 0
- 44. CIRCULAR SHIFT <ul><li>In a circular shift the serial input is the bit that is shifted out of the other end of the register. </li></ul><ul><li>A right circular shift operation: </li></ul><ul><li>A left circular shift operation: </li></ul><ul><li>In a RTL, the following notation is used </li></ul><ul><ul><li>cil for a circular shift left </li></ul></ul><ul><ul><li>cir for a circular shift right </li></ul></ul><ul><ul><li>Examples: </li></ul></ul><ul><ul><ul><li>R2 cir R2 </li></ul></ul></ul><ul><ul><ul><li>R3 cil R3 </li></ul></ul></ul>Shift Microoperations Prof. RAKESH ROSHAN 09971640291
- 45. ARITHMETIC SHIFT <ul><li>An arithmetic shift is meant for signed binary numbers (integer) </li></ul><ul><li>An arithmetic left shift multiplies a signed number by two </li></ul><ul><li>An arithmetic right shift divides a signed number by two </li></ul><ul><li>The main distinction of an arithmetic shift is that it must keep the sign of the number the same as it performs the multiplication or division </li></ul><ul><li>A right arithmetic shift operation: </li></ul><ul><li>A left arithmetic shift operation: </li></ul>Shift Microoperations sign bit sign bit Prof. RAKESH ROSHAN 09971640291 0
- 46. ARITHMETIC SHIFT Shift Microoperations <ul><li>In a RTL, the following notation is used </li></ul><ul><ul><li>ashl for an arithmetic shift left </li></ul></ul><ul><ul><li>ashr for an arithmetic shift right </li></ul></ul><ul><ul><li>Examples: </li></ul></ul><ul><ul><ul><li>R2 ashr R2 </li></ul></ul></ul><ul><ul><ul><li>R3 ashl R3 </li></ul></ul></ul>Prof. RAKESH ROSHAN 09971640291
- 47. HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONS Shift Microoperations A combinational circuit shifter can be constructed with multiplexers. The 4-bit shifter has four Data inputs, A0 through A3 and four data outputs, H0 through H3. There are two serial inputs, one For shift left (IL) and the other for shift right (IR). When the selection input S=0 , the input data are Shifted right (down in the diagram). When S=1, the input data are shifted left(up in the diagram). The function table shows which input goes to each output after the shift. A shifter with n data and Outputs requires n multiplexers. The two serial inputs can be controlled another multiplexer to Provide the three possible types of shifts. Prof. RAKESH ROSHAN 09971640291 S 0 1 H0 MUX S 0 1 H1 MUX S 0 1 H2 MUX S 0 1 H3 MUX Select 0 for shift right (down) 1 for shift left (up) Serial input (I R ) A0 A1 A2 A3 Serial input (I L ) Select Output S H0 H1 H2 H3 0 I R A0 A1 A2 1 A1 A2 A3 I L
- 48. ARITHMETIC LOGIC SHIFT UNIT <ul><ul><li>S3 S2 S1 S0 Cin Operation Function </li></ul></ul><ul><ul><li>0 0 0 0 0 F = A Transfer A </li></ul></ul><ul><ul><li>0 0 0 0 1 F = A + 1 Increment A </li></ul></ul><ul><ul><li>0 0 0 1 0 F = A + B Addition </li></ul></ul><ul><ul><li>0 0 0 1 1 F = A + B + 1 Add with carry </li></ul></ul><ul><ul><li>0 0 1 0 0 F = A + B’ Subtract with borrow </li></ul></ul><ul><ul><li>0 0 1 0 1 F = A + B’+ 1 Subtraction </li></ul></ul><ul><ul><li>0 0 1 1 0 F = A - 1 Decrement A </li></ul></ul><ul><ul><li>0 0 1 1 1 F = A TransferA </li></ul></ul><ul><ul><li>0 1 0 0 X F = A B AND </li></ul></ul><ul><ul><li>0 1 0 1 X F = A B OR </li></ul></ul><ul><ul><li>0 1 1 0 X F = A B XOR </li></ul></ul><ul><ul><li>0 1 1 1 X F = A’ Complement A </li></ul></ul><ul><ul><li>1 0 X X X F = shr A Shift right A into F </li></ul></ul><ul><ul><li>1 1 X X X F = shl A Shift left A into F </li></ul></ul>Shift Microoperations The arithmetic, logic and shift circuits can be combined into One ALU with common selection variables. The subscript i Designates a typical stage. Input A i and B i are applied to both the arithmetic and logic units. A particular microoperation is selected with inputs S1 and S0. A 4*1 multiplexer at the output chooses between an arithmetic output in E i and a logic output in Hi. The data in the multiplexer are selected with S3 and S2. The other two data inputs to the multiplexer receive inputs A i-1 for the shift-left operation. The output carry C i+1 of a given arithmetic stage must be connected to the input carry C i of the next stage in sequence. The input carry to the first stage is the input carry C in , which provides a selection variable for The arithmetic operations. Prof. RAKESH ROSHAN 09971640291 Arithmetic Circuit Logic Circuit C C 4 x 1 MUX Select 0 1 2 3 F S3 S2 S1 S0 B A i A D A E shr shl i+1 i i i i+1 i-1 i i
- 49. Design of Fast adder (Carry- Lookahead Addition) A fast adder circuit must speed up the generation of the carry signals. The logic expressions for s i (sum) and c i+1 (carry out) of stage i are si=xi yi zi And ci+1=xiyi+xici+yici Factoring the second equation into ci+1=xiyi+(xi+yi)ci We can write ci+1=Gi and Pici Where Gi=xiyi and Pi=xi+yi The expression Gi and Pi are called the generate and propagate functions of stage i. If the generate function for stage I is equal to 1, then ci+1=1, independent of the input carry ci. This occurs when both xi and yi are 1. The propagate function means that an input carry will produce an output carry when either xi is 1 or yi is 1. All Gi and Pi functions can be formed independently and in parallel in one logic gate delay after the X and Y vectors are applied to the inputs of an n-bit adder. Prof. RAKESH ROSHAN 09971640291
- 50. Design of Fast adder (Carry- Lookahead Addition) A fast adder circuit must speed up the generation of the carry signals. The logic expressions for s i (sum) and c i+1 (carry out) of stage i are si=xi yi zi And ci+1=xiyi+xici+yici Factoring the second equation into ci+1=xiyi+(xi+yi)ci We can write ci+1=Gi and Pici Where Gi=xiyi and Pi=xi+yi Expanding ci in terms of i-1 subscripted variables and substituting into the ci+1 Expression, we obtain ci+1=Gi+PiGi-1 + PiPi-1ci-1 Continuing this type of expansion, the final expression for any carry variable is ci+1=Gi+PiGi-1 + PiPi-1Gi-2+……….+PiPi-1….P1G0+PiPi…….P0c0 Example:- c1=G0+Poc0 c2=G1+P1G0+P1P0c0 c3=G2+P2G1+P2P1G0+P2P1P0c0 c4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0c0 The carries are implemented in the block labeled carry- lookahead logic. An adder implemented in this form is called a carry- lookahead adder. Prof. RAKESH ROSHAN 09971640291
- 51. 4-bit Carry- lookahead adder c0 s3 Where P 0 I =P 3 P 2 P 1 P 0 and G 0 I =G 3 +P 3 G 2 +P 3 P 2 P 1 G 0 Prof. RAKESH ROSHAN 09971640291 Carry- look ahead logic B cell B cell B cell B cell x3 y3 x2 y2 x1 y1 x0 y0 c3 c2 c1 s3 s2 s1 s0 c4 G3 G2 G1 G0 P3 P2 P1 P0 G 0 I P 0 I
- 52. Addition and Subtraction Algorithm Minuend in A Subtrahend in B Augend in A Addend in B As Bs As Bs EA A+B’+1 AVF 0 EA A+B E AVF E A A A’ A A+1 As As As 0 END (result is in A and As) Subtraction Operation Add Operation 1 0 1 0 0 1 !=0 0 A<B A>=B As=Bs As!=Bs As!=Bs As=Bs Prof. RAKESH ROSHAN 09971640291
- 53. Booth Multiplication Algorithm Multiply Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement representation Prof. RAKESH ROSHAN 09971640291 Multiplicand in BR Multiplier in QR AC 0 Qn+1 o SC n QnQn+1 AC AC-BR AC AC+BR Ashr(AC & QR) SC SC-1 SC END 10 01 00 11 !=0 0
- 54. Example of Multiplication with Booth algorithm Let n=5 , multiply =(-9) * (-13)=+117 Prof. RAKESH ROSHAN 09971640291 Q n Q n+1 BR=10111 (BR)’+1=01001 AC QR Q n+1 SC Initial 00000 10011 0 101 10 Subtract BR 01001 01001 Ashr 00100 11001 1 100 11 Ashr 00010 01100 1 011 01 Add BR 10111 11001 Ashr 11100 10110 0 010 00 Ashr 11110 01011 0 001 10 Subtract BR 01001 00111 Ashr 00011 10101 1 000
- 55. IEEE standard for floating numbers This standard for representing floating-point numbers in 32 bits has been developed and specifies in detail By the Institute of Electrical and Electronics Engineers(IEEE). The standard describes both the representation and the way in which the four basic arithmetic operations are to be performed. In 32-bit representation, the sign of the number is given in the first bit, followed by a representation for the exponent (to the base 2) of the Scale factor. Instead of the signed exponent, E, the value actually stored in the exponent field is an unsigned Integer E’=E+127. This is called the excess-127 format. The last 23 bits represent the mantissa. S E’ M 32 bits Sign of Number: 0 signifies + 1 signifies - 8-bit signed Exponent in Excess-127 representation 23-bit Mantissa fraction Value represented=±1.M × 2 E’-127 Example : Representation of 1.001010……….0 ×2 -87 0 00101011 . 001010………………………………………………………………0 Prof. RAKESH ROSHAN 09971640291

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