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1. Computer Organization UNIT 1 Prepared By Prof. Rakesh Roshan [email_address] n Prof. RAKESH ROSHAN 09971640291

2. REGISTER TRANSFER AND MICROOPERATIONS • Register Transfer Language • Register Transfer • Bus and Memory Transfers • Arithmetic Microoperations • Logic Microoperations • Shift Microoperations • Arithmetic Logic Shift Unit Prof. RAKESH ROSHAN 09971640291

5. MICROOPERATION (2) An elementary operation performed (during one clock pulse), on the information stored in one or more registers R  f(R, R) f: shift, load, clear, increment, add, subtract, complement, and, or, xor, … 1 clock cycle Register Transfer Language Prof. RAKESH ROSHAN 09971640291 ALU (f) Registers (R)

14. HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS Implementation of controlled transfer P: R2  R1 Block diagram Timing diagram Clock Register Transfer Transfer occurs here R2 R1 Control Circuit Load P n Clock Load t t+1 The block diagram that depicts the transfer from R1 to R2. The n outputs of register R1 are connected to the n inputs of register R2. The letter n will be used to indicate any number of bits for the register. It will be replaced by an actual number when the length Of the register is known. Register R2 has load input that is activated by the control variable P. In timing diagram , P is activated in the control section by the rising edge of a clock pulse at time t. The next positive transition of the clock at time t+1 finds the load active and the data inputs of R2 are then loaded into the register in parallel. P may go back to 0 at Time t+1; otherwise, the transfer will occur with every clock pulse transition while P remains active. Prof. RAKESH ROSHAN 09971640291

16. BASIC SYMBOLS FOR REGISTER TRANSFERS Capital letters Denotes a register MAR, R2 & numerals Parentheses () Denotes a part of a register R2(0-7), R2(L) Arrow   Denotes transfer of information R2  R1 Colon : Denotes termination of control function P: Comma , Separates two micro-operations A  B, B  A Symbols Description Examples Register Transfer Prof. RAKESH ROSHAN 09971640291

18. Bus System for four registers From a register to bus: BUS  R Bus and Memory Transfers We can construct the common bus system is with multiplexers. The multiplexers select the source Register whose binary information is then placed on the bus. Prof. RAKESH ROSHAN 09971640291 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 Register A Register B Register C Register D B C D 1 1 1 4 x1 MUX B C D 2 2 2 4 x1 MUX B C D 3 3 3 4 x1 MUX B C D 4 4 4 4 x1 MUX 4-line bus x y select 0 0 0 0 Register A Register B Register C Register D Bus lines x y Register Selected 0 0 A 0 1 B 1 0 C 1 1 D

19. TRANSFER FROM BUS TO A DESTINATION REGISTER Three-State Bus Buffers Bus line with three-state buffers Output Y=A if C=1 High-impedence if C=0 Normal input A Control input C Select Enable 0 1 2 3 S0 S1 A0 B0 C0 D0 Bus line for bit 0 Bus and Memory Transfers A bus system can be constructed with three-state gated instead of multiplexers. A three-state gate Is a digital circuit that exhibits three states. Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate. The third state is a high-impedance state. The high-impedance state Behaves like an open circuit, which means that the output is disconnected and does not have A logic significance. Three-state gates may perform any conventional logic, such as AND and NAND. However, the one most commonly used in the design of a bus system is the buffer gate. In the above diagram, The outputs of four buffers are connected together to form a single bus line . The control inputs to the buffers determine which of the four normal inputs will communicate With the bus line. No more than one buffer may be in the active state at any given time. The Connected buffers must be controlled so that only one three-state buffer has access to the bus line while all other buffers are maintained in a high impedance state. Prof. RAKESH ROSHAN 09971640291

25. SUMMARY OF R. TRANSFER MICROOPERATIONS Bus and Memory Transfers A  B Transfer content of reg. B into reg. A AR  DR(AD) Transfer content of AD portion of reg. DR into reg. AR A  constant Transfer a binary constant into reg. A ABUS  R1, Transfer content of R1 into bus A and, at the same time, R2  ABUS transfer content of bus A into R2 AR Address register DR Data register M[R] Memory word specified by reg. R M Equivalent to M[AR] DR  M Memory read operation: transfers content of memory word specified by AR into DR M  DR Memory write operation: transfers content of DR into memory word specified by AR Prof. RAKESH ROSHAN 09971640291

28. BINARY ADDER / SUBTRACTOR / INCREMENTER Binary Adder-Subtractor Binary Adder Arithmetic Microoperations The addition and subtraction operations can be combined into one common circuit by including An exclusive-OR gate with full adder. In 4-bit adder-subtractor circuit, the mode input M controls The operation. When M=0 the circuit is an adder and when M=1 the circuit becomes a subtractor. Each exclusive-OR gate receive input M and one of the inputs of B. When M=0, we have B 0=B. The full adders receives the value of B, input carry is 0, and the circuit performs A plus B. When M=1 we have B 1=B’ and C0 = 1. The B inputs are all complemented and a 1 is added through The input carry. The circuit performs the operation A plus the 2’s complement of B. Prof. RAKESH ROSHAN 09971640291

30. ARITHMETIC CIRCUIT S1 S0 Cin Y Output Microoperation 0 0 0 B D = A + B Add 0 0 1 B D = A + B + 1 Add with carry 0 1 0 B’ D = A + B’ Subtract with borrow 0 1 1 B’ D = A + B’+ 1 Subtract 1 0 0 0 D = A Transfer A 1 0 1 0 D = A + 1 Increment A 1 1 0 1 D = A - 1 Decrement A 1 1 1 1 D = A Transfer A Arithmetic Microoperations Prof. RAKESH ROSHAN 09971640291 S1 S0 0 1 2 3 4x1 MUX X0 Y0 C0 C1 D0 FA S1 S0 0 1 2 3 4x1 MUX X1 Y1 C1 C2 D1 FA S1 S0 0 1 2 3 4x1 MUX X2 Y2 C2 C3 D2 FA S1 S0 0 1 2 3 4x1 MUX X3 Y3 C3 C4 D3 FA Cout A0 B0 A1 B1 A2 B2 A3 B3 0 1 S0 S1 Cin

34. HARDWARE IMPLEMENTATION OF LOGIC MICROOPERATIONS 0 0 F = A  B AND 0 1 F = A  B OR 1 0 F = A  B XOR 1 1 F = A’ Complement S 1 S 0 Output  -operation Function table Logic Microoperations Prof. RAKESH ROSHAN 09971640291 B A S S F 1 0 i i i 0 1 2 3 4 X 1 MUX Select

47. HARDWARE IMPLEMENTATION OF SHIFT MICROOPERATIONS Shift Microoperations A combinational circuit shifter can be constructed with multiplexers. The 4-bit shifter has four Data inputs, A0 through A3 and four data outputs, H0 through H3. There are two serial inputs, one For shift left (IL) and the other for shift right (IR). When the selection input S=0 , the input data are Shifted right (down in the diagram). When S=1, the input data are shifted left(up in the diagram). The function table shows which input goes to each output after the shift. A shifter with n data and Outputs requires n multiplexers. The two serial inputs can be controlled another multiplexer to Provide the three possible types of shifts. Prof. RAKESH ROSHAN 09971640291 S 0 1 H0 MUX S 0 1 H1 MUX S 0 1 H2 MUX S 0 1 H3 MUX Select 0 for shift right (down) 1 for shift left (up) Serial input (I R ) A0 A1 A2 A3 Serial input (I L ) Select Output S H0 H1 H2 H3 0 I R A0 A1 A2 1 A1 A2 A3 I L

49. Design of Fast adder (Carry- Lookahead Addition) A fast adder circuit must speed up the generation of the carry signals. The logic expressions for s i (sum) and c i+1 (carry out) of stage i are si=xi yi zi And ci+1=xiyi+xici+yici Factoring the second equation into ci+1=xiyi+(xi+yi)ci We can write ci+1=Gi and Pici Where Gi=xiyi and Pi=xi+yi The expression Gi and Pi are called the generate and propagate functions of stage i. If the generate function for stage I is equal to 1, then ci+1=1, independent of the input carry ci. This occurs when both xi and yi are 1. The propagate function means that an input carry will produce an output carry when either xi is 1 or yi is 1. All Gi and Pi functions can be formed independently and in parallel in one logic gate delay after the X and Y vectors are applied to the inputs of an n-bit adder. Prof. RAKESH ROSHAN 09971640291

50. Design of Fast adder (Carry- Lookahead Addition) A fast adder circuit must speed up the generation of the carry signals. The logic expressions for s i (sum) and c i+1 (carry out) of stage i are si=xi yi zi And ci+1=xiyi+xici+yici Factoring the second equation into ci+1=xiyi+(xi+yi)ci We can write ci+1=Gi and Pici Where Gi=xiyi and Pi=xi+yi Expanding ci in terms of i-1 subscripted variables and substituting into the ci+1 Expression, we obtain ci+1=Gi+PiGi-1 + PiPi-1ci-1 Continuing this type of expansion, the final expression for any carry variable is ci+1=Gi+PiGi-1 + PiPi-1Gi-2+……….+PiPi-1….P1G0+PiPi…….P0c0 Example:- c1=G0+Poc0 c2=G1+P1G0+P1P0c0 c3=G2+P2G1+P2P1G0+P2P1P0c0 c4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0c0 The carries are implemented in the block labeled carry- lookahead logic. An adder implemented in this form is called a carry- lookahead adder. Prof. RAKESH ROSHAN 09971640291

51. 4-bit Carry- lookahead adder c0 s3 Where P 0 I =P 3 P 2 P 1 P 0 and G 0 I =G 3 +P 3 G 2 +P 3 P 2 P 1 G 0 Prof. RAKESH ROSHAN 09971640291 Carry- look ahead logic B cell B cell B cell B cell x3 y3 x2 y2 x1 y1 x0 y0 c3 c2 c1 s3 s2 s1 s0 c4 G3 G2 G1 G0 P3 P2 P1 P0 G 0 I P 0 I

52. Addition and Subtraction Algorithm Minuend in A Subtrahend in B Augend in A Addend in B As Bs As Bs EA  A+B’+1 AVF  0 EA  A+B E AVF  E A A  A’ A  A+1 As  As As  0 END (result is in A and As) Subtraction Operation Add Operation 1 0 1 0 0 1 !=0 0 A<B A>=B As=Bs As!=Bs As!=Bs As=Bs Prof. RAKESH ROSHAN 09971640291

53. Booth Multiplication Algorithm Multiply Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement representation Prof. RAKESH ROSHAN 09971640291 Multiplicand in BR Multiplier in QR AC  0 Qn+1  o SC  n QnQn+1 AC  AC-BR AC  AC+BR Ashr(AC & QR) SC  SC-1 SC END 10 01 00 11 !=0 0

54. Example of Multiplication with Booth algorithm Let n=5 , multiply =(-9) * (-13)=+117 Prof. RAKESH ROSHAN 09971640291 Q n Q n+1 BR=10111 (BR)’+1=01001 AC QR Q n+1 SC Initial 00000 10011 0 101 10 Subtract BR 01001 01001 Ashr 00100 11001 1 100 11 Ashr 00010 01100 1 011 01 Add BR 10111 11001 Ashr 11100 10110 0 010 00 Ashr 11110 01011 0 001 10 Subtract BR 01001 00111 Ashr 00011 10101 1 000

55. IEEE standard for floating numbers This standard for representing floating-point numbers in 32 bits has been developed and specifies in detail By the Institute of Electrical and Electronics Engineers(IEEE). The standard describes both the representation and the way in which the four basic arithmetic operations are to be performed. In 32-bit representation, the sign of the number is given in the first bit, followed by a representation for the exponent (to the base 2) of the Scale factor. Instead of the signed exponent, E, the value actually stored in the exponent field is an unsigned Integer E’=E+127. This is called the excess-127 format. The last 23 bits represent the mantissa. S E’ M 32 bits Sign of Number: 0 signifies + 1 signifies - 8-bit signed Exponent in Excess-127 representation 23-bit Mantissa fraction Value represented=±1.M × 2 E’-127 Example : Representation of 1.001010……….0 ×2 -87 0 00101011 . 001010………………………………………………………………0 Prof. RAKESH ROSHAN 09971640291