Dual Edge trigger flip-flop on cadence virtuoso tool

1. A presentation on
NEW LOW GLITCH AND LOW POWER DET
FLIP-FLOPS USING MULTIPLE C-ELEMENT
Under the guidance of
Dr. D. Vaithiyanathan
Department of Electronics and Communication
Engineering
National Institute of Technology, Delhi
Presented by:
Yogesh Pal (172221013)
M. Tech. (VLSI)

2. INTRODUCTION
 Flip-Flop have a great impact on circuit power
consumption and speed.
 Improving the performance one innovating approach is
to increase the clock frequency.
 Using high clock frequency Power consumption of
the clock system increases.

3. DUAL EDGE TRIGGER FLIP-FLOP
 The dual edge trigger flip-flop are sequential element
which are capable of capturing data on both rising and
falling edges of the clock. Such storage elements are
termed as Dual-Edge Triggered Flip-Flops (DETFFs).

4. CONTI….
 Dual edge clocking can be used to saved half of
the power in the clock distribution network. The
average power in a digital CMOS circuit is given
by the following equation :
Pavg = CL*Vdd^2* fclk + Isc*Vdd + I leakage*Vdd

5. C-ELEMENT
Figure : The transistor level schematic of the weak feedback C-element
•A three-terminal device
•When all of its inputs
are the same, the output
switches to the value of
the inputs
• When the inputs are not
the same, the previous
output value is
preserved.

6. LG_C DET FLIP-FLOPS
Figure : LG_C DET FLIP-FLOP using weak feedback C-element

7. IMPLICIT PULSED IP_C DET FLIP_FLOPS
Figure : IP_C DET Flip-Flop

8. FLOATING NODE FN_C DET FLIP-FLOP
Figure: Floating node FN_C DET flip-flops

9. CONDITIONAL TOGGLE CT_C FLIP-FLOP
Figure: Conditional toggle CT_C flip-flops

10. CONDITIONAL TOGGLE CTF_C DET FLIP-FLOPS
Figure: Conditional toggle CTF_C DET flip-flops

11. Comparison with different DET flip-flops

12. CONCLUSION
 In this project comparison different DET flip-flops
using C-element technique are used for reducing
power consumption and delay at 90nm CMOS
technology.
 These circuit are used in
Shift Register
Counter
Memories

13. REFRENCE
 Stepan Lapshev and S. M. Rezaul Hasan, Senior Member, IEEE “New Low Glitch
and Low Power DET Flip-Flops Using Multiple C-Elements” IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL.
63, NO. 10, OCTOBER 2016
 M. Alioto, E. Consoli, and G. Palumbo, “Analysis and comparison of variations in
double edge triggered flip-flops,” in Proc. 5th Eur. Workshop CMOS Variability
(VARI), Palma de Mallorca, Spain, 2014, pp. 1–6.
 S.V. Devarapalli, P.Zarkesh-Ha, and S.C. Suddarth, “A robust and low power dual
data rate (DDR) flip-flop using C-elements,”in Proc. 11th Int Symp. Quality Electron.
Des. (ISQED), Mar. 22-24 2010, pp,147-150.
 N. Nedovic and V.G. Oklobdzija, “Dual-edge triggered storage elements and clocking
strategy for low-power systems,” IEEE Trans. Very Large Scale Integr.(VLSI)Syst.,
vol. 13,no.5,pp.577-590,May 2005.
 A. G. M. Strollo, E. Napoli, and C. Cimino, “Analysis of power dissipation in double
edge-triggered flip-flops,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8,
no. 5, pp. 624–629, Oct. 2000

14. THANK YOU