1. A Simulation study of zinc oxide nanowire field-effect transistors (znonwfets)

2. Outline nanowireMG – 3-D NWFET simulator Short Channel Effects (SCEs) Zinc Oxide (ZnO) ZnO Nanodevices NWFET Simulations & Results Conclusions Future Work

3. nanowireMG – 3D simulations To fully understand device performance and underlying physics at quantum level Planar MOSFETs – uniform charge/potential profiles in transverse direction NWFETs – 3D distribution of electron density and potential Confinement and tunneling effects

4. nanowireMG – 3D simulations Effective Mass Theory (EMT) Product-space method – 2D Non-Equilibrium Green’s Function (NEGF) – 1D Shin, M. Mathematics and Computers in Simulation; 2007

5. SS increase Short-Channel Effects (SCEs) Channel Length Modulation Subthreshold Swing Degradation Drain Induced Barrier Lowering (DIBL) Iwai et al. Microelectronics Reliability, 2002; 42:465:491Taur et al. Advanced Semiconductor and Organic Nano-Techniques; 2003: 211-238

6. Short-Channel Effects (SCEs) DIBL and threshold voltage roll-off SS degradation Park, J.-T. et al. IEEE Transactions on Electron Devices; 2002; 49: 2222-9.Colinge J. Solid-State Electronics; 2004;48 :897-905.

7. Zinc Oxide (ZnO) Cubic zincblende Rock salt (NaCl) Hexagonal wurtzite (P63mc) Jagadish et al. Zinc Oxide Bulk, Thin Film & Nanostructures

8. ZnO - Properties Eg~ 3.4 eV (direct) Transparent to visible light Operation in UV/blue light regime (356 – 446 nm) Bandgap engineering (CdO, MgO) Exciton binding energy 60 meV (28 meV – GaN) ↑ luminescence efficiency High optical gain 300 cm-1 (100 cm-1GaN) http://www.photonics.com/content/spectra/2006/April/LED/82170.aspx Norris B. J Phys D. 2003,36:L105-7

10. ZnO NW Synthesis Vapor-Liquid-Solid (VLS) method Chemical Vapor Deposition (CVD) Metal Organic Vapor-Phase Epitaxy (MOVPE) Jagadish et al. Zinc Oxide Bulk, Thin Film & Nanostructures

11. ZnO Nanodevices Park et al. Advanced Materials (2004), 16:87 Park et al. Advanced Materials (2005), 17:1393-7

12. ZnO NWFET Simulations

13. Gate Configuration NW diameter W = T = 25 nm Lc = Lg = 50 nm Tox = 1 nm Colinge J.FinFETs & Other Multi-Gate Transistors. 2008.

14. Single-Gate  Quad-Gate 53 mV/dec 200 mV/dec Single-Gate Quad-Gate SS at Vd = 0.75 V; ballistic transport assumption Depletion-type FET behavior

15. Single-Gate  Quad-Gate Double Single-Gate GAA Id-Vg curves at Vd = 0.75 V GAA > Omega- > Pi- > Tri- > Double- > Single-Gate

16. Gate Configuration

17. NW Diameter Variations d = 50 nm Quad-Gate d = 5 nm SS improvement Lowering of on-state/saturation currents ~ order of magnitude

18. NW Diameter Variations 100 SS 62 Id,sat SS improvement ~ factor of 2 Id,sat lowering reduction in cross-sectional area

19. Gate Length Variation 5 nm 15 nm SimulatedSi NWFETs GAA NWFET with Lc = Lg Lower off-state currents for longer gate transistors Larger source-drain tunneling distance; (Itunn/Id)

20. Gate Length Variation TRI PI PI GAA (Si) GAA SS improves from 120 mV/dec 60 mV/dec DIBL improvement as well 200 mV/V  20 mV/V

21. Aspect Ratio Variation ZnONWFET Simulated Si NWFET L/W = 1, 1.5, 2 for W = 5, 8, 10 nm Performance improves for greater L/W

22. Aspect Ratio – ZnO/Si comparison L/W = 2 L/W = 1.5 L/W = 1

23. Aspect Ratio – SS SS improves from 110 mV/dec 65 mV/dec

24. Gate Underlap ZnONWFET 0 nm 2.5 nm Simulated ZnO NWFET 5 nm GIDL: Band-to-band tunneling is a function of total electric field in the drain overlap region Lg = W = T = 5 nm (GAA) Gate underlaps 0, 2.5, 5 nm

25. Gate Underlap Lowering of on-state currents SS falls below the acceptable value of 100 mV/decade for transistors having gate underlap

26. Conclusions Device modeling to assess performance of potential ZnO NWFETs Quantum mechanics including ballistic transport Near ideal subthreshold characteristics (SS, DIBL) Gate length  15 nm Gate underlap  5 nm Aspect ratio (L/W)  2 Gate configuration  Quad-Gate (Gate-All-Around) Nanowire diameter  5 nm On-state currents could be improved by fabricating parallel arrays of nanowire FETs.

27. Future Work Ballistic transport represents upper limit to device performance Inclusion of carrier scattering and contact resistance would provide a more practical model of NWFET simulation Limitation on maximum size of simulated NWFET Increase software’s maximum allowable values for device parameters Integrating multiple nanowires in FET simulations Increases on-currents

28. Questions?