5. • Definition of counter:
• A digital device which count the clock pulses
sent at its clock point. These pulses are count
pulses .
• The counters have sequential circuits which
produce output based on count pulses applied
on it.
• Counters are constructed using J-K / T flip flops.
• Normally a counter count the count pulses in
binary form but can be modified to count in
BCD code also or any other possible code.
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6. • Types of counters: Two type:
• 1)asynchronous and 2) Synchronous.
• Asynchronous counters:
• These are simple in design.
• Require more time or more clock pulses to
produce the output.
• Settling time is more.
• If the counter requires multi flip flops to
accomplish the design then clock pulse is given
to starting flip flop only , other flip flop in the
design gets the clock from the Q or Q’ output of
previous flip flop, meaning all the flip flops in 6
7. • The design are not triggered from same clock.
• Triggering the first flip flop only by the count
pulse and then triggering other flip flops from
the outputs will cause the delay in getting
required output.
• This delay is called propagation delay. More
number of the flip flops in the design means
large delay.
• These counters are succumbed to glitches.
• Asynchronous counters are also called Ripple
counters.
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8. • Synchronous counters:
• Complex design.
• Requires single clock or less clocks to produce
output.
• Settling time is very less.
• If the counter requires multi flip flops to
accomplish the design then clock pulse is given
to all flip flops simultaneously, meaning all the
flip flops in the design are triggered from same
clock. So output is available from all flip flop
simultaneously.
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9. • Immediate output means very low propagation
delay. So speed is high.
• Glitches problem does not arrive.
• Counting in codes other then binary make the
ripple counter very cumbersome , while it is
straight forward in designing with synchronous
counters.
• Synchronous counters can start counting from
any random number up to any random number
in sequence or out of sequence.
• Need a systematic procedure to design
synchronous counters. 9
10. • Asynchronous counter: Single bit:
• One bit so one flip flop required:
• Two bit so two flip flop required:
• Note: use slide show for current slide.
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Q’
CLK
Q’
Q
T=1 Q
CLK
T=1
0
0
1
01
11. • Asynchronous counter: Single bit:
• One bit so one flip flop required:
•
11
Q’
CLK
Q’
Q
T=1 Q
CLK
T=1
0
0
1
01
12. • This is the end of topic 5.
• Will continue from here in topic 6
Thank You
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