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Asynchronous Counters
Lecture Overview
 Classifications of Counters
 Definitions
 Asynchronous Counter…
 J – K Flip Flops
 D Flip Flops
 Up Counters
 Down Counters
 Truncated Counters
 Design Example
Classifications of Counters
Asynchronous Counters
 Only the first flip-flop is clocked by an external
clock. All subsequent flip-flops are clocked by the
output of the preceding flip-flop.
 Asynchronous counters are slower than
synchronous counters because of the delay in
the transmission of the pulses from flip-flop to
flip-flop.
 Asynchronous counters are also called ripple-
counters because of the way the clock pulse
ripples it way through the flip-flops.
Classifications of Counters
Synchronous Counters
 All flip-flops are clocked simultaneously by an
external clock.
 Synchronous counters are faster than
asynchronous counters because of the
simultaneous clocking.
 Synchronous counters are an example of state
machine design because they have a set of
states and a set of transition rules for moving
between those states after each clocked event.
States / Modulus / Flip-Flops
 The number of flip-flops determines the count
limit or number of states.
(STATES = 2 # of flip flops
)
 The number of states used is called the
MODULUS.
 For example, a Modulus-12 counter would
count from 0 (0000) to 11 (1011) and requires
four flip-flops (16 states - 12 used).
1 Bit Asynch-Counter / Modulus 2
2 Bit Asynch-Counter / Modulus 4
3 Bit Asynch-Counter / Modulus 8
The Ripple Effect…
Q0
Q1
Q2
Ripple Effect…The Problem
Q0
Q1
Q2
3 4
2 0
D Flip-Flop… Nothing Special About J-K
Six Examples
1. Modulus 4 Up Counter with Negative
Edge Triggered Flip-Flops
2. Modulus 4 Down Counter with Negative
Edge Triggered Flip-Flops
3. Modulus 4 Up Counter with Positive
Edge Triggered Flip-Flops
4. Modulus 4 Down Counter with Positive
Edge Triggered Flip-Flops
5. Truncated Counter
6. Counter Design
Up Counter w/ Negative Edge Flip-Flops
Down Counter w/ Negative Edge Flip-Flops
Up Counter w/ Positive Edge Flip-Flops
Down Counter w/ Positive Edge Flip-Flops
Truncating the Count… Modulus 6
Modulus-6 Counter
Asynchronous Counter Design Steps
1. Select Type
 Up or Down
 Modules
2. Select Flip-Flop Type
 J-K or D
 Positive Edge Trigger (PET) or Negative Edge
Trigger (NET)
3. Determine Number of Flip-Flops
 (2
# Flip-Flop
 Modules)
Asynchronous Counter Design Steps
5. Design Basic Counters
 Same polarity for down counters:
 Opposite polarity for up counters:
6. Design Limits Logic
 Input to logic is count that is one past the end
of sequence.
NET
Q
or
PET
Q 

PET
Q
or
NET
Q 

Design Example
1. Select Type
 Up or Down
 Modules
2. Select Flip-Flop Type
 J-K or D
 Positive Edge Trigger (PET) or Negative Edge
Trigger (NET)
3. Determine Number of Flip-Flops
 (2
# Flip-Flop
 Modules)
MOD – 14 (0..13)
24 Flip-Flop
 16
Design Example
5. Design Basic Counters
 Same polarity for down counters:
 Opposite polarity for up counters:
6. Design Limits Logic
 Input to logic is count that is one past the end
of sequence.
NET
Q
or
PET
Q 

PET
Q
or
NET
Q 

Limit 13+1 = 14 (1110)
Design Example…Solution

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Lesson_8_2--Asynchronous_Counters1.ppt

  • 2. Lecture Overview  Classifications of Counters  Definitions  Asynchronous Counter…  J – K Flip Flops  D Flip Flops  Up Counters  Down Counters  Truncated Counters  Design Example
  • 3. Classifications of Counters Asynchronous Counters  Only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.  Asynchronous counters are slower than synchronous counters because of the delay in the transmission of the pulses from flip-flop to flip-flop.  Asynchronous counters are also called ripple- counters because of the way the clock pulse ripples it way through the flip-flops.
  • 4. Classifications of Counters Synchronous Counters  All flip-flops are clocked simultaneously by an external clock.  Synchronous counters are faster than asynchronous counters because of the simultaneous clocking.  Synchronous counters are an example of state machine design because they have a set of states and a set of transition rules for moving between those states after each clocked event.
  • 5. States / Modulus / Flip-Flops  The number of flip-flops determines the count limit or number of states. (STATES = 2 # of flip flops )  The number of states used is called the MODULUS.  For example, a Modulus-12 counter would count from 0 (0000) to 11 (1011) and requires four flip-flops (16 states - 12 used).
  • 6. 1 Bit Asynch-Counter / Modulus 2
  • 7. 2 Bit Asynch-Counter / Modulus 4
  • 8. 3 Bit Asynch-Counter / Modulus 8
  • 11. D Flip-Flop… Nothing Special About J-K
  • 12. Six Examples 1. Modulus 4 Up Counter with Negative Edge Triggered Flip-Flops 2. Modulus 4 Down Counter with Negative Edge Triggered Flip-Flops 3. Modulus 4 Up Counter with Positive Edge Triggered Flip-Flops 4. Modulus 4 Down Counter with Positive Edge Triggered Flip-Flops 5. Truncated Counter 6. Counter Design
  • 13. Up Counter w/ Negative Edge Flip-Flops
  • 14. Down Counter w/ Negative Edge Flip-Flops
  • 15. Up Counter w/ Positive Edge Flip-Flops
  • 16. Down Counter w/ Positive Edge Flip-Flops
  • 19. Asynchronous Counter Design Steps 1. Select Type  Up or Down  Modules 2. Select Flip-Flop Type  J-K or D  Positive Edge Trigger (PET) or Negative Edge Trigger (NET) 3. Determine Number of Flip-Flops  (2 # Flip-Flop  Modules)
  • 20. Asynchronous Counter Design Steps 5. Design Basic Counters  Same polarity for down counters:  Opposite polarity for up counters: 6. Design Limits Logic  Input to logic is count that is one past the end of sequence. NET Q or PET Q   PET Q or NET Q  
  • 21. Design Example 1. Select Type  Up or Down  Modules 2. Select Flip-Flop Type  J-K or D  Positive Edge Trigger (PET) or Negative Edge Trigger (NET) 3. Determine Number of Flip-Flops  (2 # Flip-Flop  Modules) MOD – 14 (0..13) 24 Flip-Flop  16
  • 22. Design Example 5. Design Basic Counters  Same polarity for down counters:  Opposite polarity for up counters: 6. Design Limits Logic  Input to logic is count that is one past the end of sequence. NET Q or PET Q   PET Q or NET Q   Limit 13+1 = 14 (1110)