07_Digital timing_&_Pipelining.ppt

Delay Time
Def: Time required for output signal Y
to change due to change in input signal
X
Up to now, we have assumed this delay
time has been 0 seconds.
F(x)
X Y
t=0 t=0

Delay Time
In a “real” circuit, it will take tp
seconds for Y to change due to X
F(x)
X Y
t=0 t=tp
tp is known as the propagation delay time

Timing Diagram
We use a timing diagram to graphically
represent this delay
X
Y
time,s
time,s
t=0
t=tp
0
1
0
1
Horizontal axis = time axis
Vertical axis = Logical level axis (Logic One or Logic Zero)

Timing Diagram
We see a change in X at t=0 causes a
change in Y at t=tp
Horizontal axis = time axis
Vertical axis = Logical level axis (Logic One or Logic Zero)
X
Y
time,s
time,s
t=0
t=tp
0
1
0
1
t=T
t=T+tp

Timing Diagram
We also see a change in X at t=T
causes another change in Y at t=T+tp
We see that logic circuit F causes a delay of tp seconds in
the signal
X
Y
time,s
time,s
t=0
t=tp
0
1
0
1
t=T
t=T+tp

Simple Example – Not Gate
X Y
Let tp=2 ns
Where ns = nanosecond = 1x10-9 seconds
X
Y
time,ns
time,ns
0
2
2ns

Simple Example – 2 Not Gates
Let tp=2 ns
X
Z
4
Y
0 2 6 8 t,ns
X Z Y
Total Delay = 2ns + 2ns = 4ns
2ns
2ns
4ns

Notes:
Time axis is shared among signals
Logic levels (1 or 0) are implied, not shown
X
Z
4
Y
0 2 6 8 t,ns

Sometimes dashed vertical lines are added to aid reading
diagram
X
Z
4
Y
0 2 6 8 t,ns
2ns 2ns 2ns 2ns 2ns

Where does this delay come
from?
Circuit Delay

Circuit Delay
All electrical circuits have intrinsic
resistance (R) and capacitance (C).
C R
Let’s analyze a simple RC circuit

Circuit Delay – Simple RC Circuit
R
C
Vin(t)
Vout(t)
  1 exp
out dd
t
V t V
RC


 
 
  
 
 
 
 

0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5 6 7
Vout
Vin
 
 
 
0.69 0.5
2.3 0.9
4.6 0.99
x out x dd
x out x dd
x out x dd
t V t V
t V t V
t V t V



 
 
 
Note:
timeconstant
RC
  

Circuit Delay – Example
R
C
Vin(t)
Vout(t)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5 6 7
Vout
Vin
Let R=1ohm, C=1F, so that RC=1 second
Time Delay is 0.7s or 700 ms for 0.5Vdd
Time Delay is 2.3s for 0.9Vdd
Time Delay is 4.6s for 0.99 Vdd

How do we relate this to logic
diagrams?

Def: tplh
tplh = low-to-high propagation delay time
This is the time required for the output to rise from 0V to ½ VDD
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5 6 7
tplh

Def: tphl
Tphl = high-to-low propagation delay time
This is the time required for the output to fall from Vdd to ½ VDD
tphl
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5 6 7

Def: tp
(propagation delay time)
Let’s define tp = propagation delay time as
 
1
2
p plh phl
t t
  
This will be the “average” delay through the circuit

Gate Delay – Simple RC Model
R
Vin(t)
Vout(t)
C
Vout(t)
Vin(t)
Ideal gate with RC network Equivalent model with
Gate delay of tp_not
Ideal gate with tp=0 delay
RC network
Tp=tp_not

Gate Delay - Example
X
0 25ns
0 5ns 30ns
Y
X Y
5ns
tp_not
We indicate tp on the gate

Combinational Logic Delay
A
B
C
D
Y
5ns
5ns
5ns
5ns
5ns
Shortest delay
Longest delay
Longest delay = 20ns
Shortest delay = 5ns
This circuit has multiple delay paths
A-Y = 5ns+5ns+5ns=15ns
B-Y = 5ns+5ns+5ns+5ns=20ns
C-Y = 5ns+5ns+5ns=15ns
D-Y = 5ns
   
 
, , ,
F a b c d D AB B C
   

Combinational Logic Delay
A
B
C
D
Y
5ns
5ns
5ns
5ns
5ns
Shortest delay
Longest delay
Longest delay = 20ns
We’ll use the longest delay to represent
the logic function F.
Let’s call it Tcl for time, combinational logic
   
 
, , ,
F a b c d D AB B C
   

Combinational Logic (CL)
Cloud Model
A
B
C
D
E
Y
5ns
5ns
5ns
5ns
5ns
F
tcl
X Y
Tcl=20ns
Tcl=20ns
   
 
, , ,
F a b c d D AB B C
   

Logic Simulators
Used to simulate the output
response of a logic circuit.

Logic Simulations
Three primary types
 Circuit simulator (e.g. PSPICE)
 “Exact” delay for each gate
 Most accurate timing analysis
 Very slow compared to other types
 Functional Simulation (e.g. Quartus )
 Assumes one unit delay for each gate
 Very fast compared to other types
 Most inaccurate timing analysis
 Timing Simulation (e.g. Quartus)
 Assumes “average” tp delay for each gate
 Not the fastest or slowest timing analysis
 Provides “pretty good” timing analysis

Calculate all delay paths through
the circuit shown below
A
B
C
D
Y
2ns
5ns
8ns
5ns
10ns
What is the shortest and longest delay?

Solution: Calculate all delay paths
through the circuit shown below
A
B
C
D
Y
2ns
5ns
8ns
5ns
10ns
This circuit has multiple delay paths
A-Y = 5ns+5ns+10ns=20ns
B-Y = 2ns+5ns+5ns+10ns=22ns
B-Y = 8ns+5ns+10ns=23ns
C-Y = 8ns+5ns+10ns=23ns
D-Y = 10ns
Shortest path=10ns
Longest path=23ns

Given the circuit below, find
(a) Expression for the logic function
(b) Longest delay in original circuit
A
C
B
2ns
5ns
7ns
7ns Y

Solution: Given the circuit below, find
(a) Original logic function
(b) Longest delay in original circuit
   
Y AC B C C
   
A
C
B
2ns
5ns
7ns
7ns Y
Longest Delay = 7ns+7ns = 14ns

Given the circuit below,
(a) Using Boolean Algebra, minimize the logic function
(b) Longest delay in minimized circuit
Delay times are
NOT gates= 2ns; AND,OR gates= 5ns
NAND, NOR gates= 7ns; XOR gates: 10ns
XNOR gates: 12ns
A
C
B
2ns
5ns
7ns
7ns Y

(a) Minimized logic function
Delay times are
XNOR gates: 12ns
A
C
B
2ns
5ns
7ns
7ns Y
You can show
Y AC


(a) Minimized logic function
Delay times are
XNOR gates: 12ns
A
C
2ns
5ns Y
Y AC

Longest delay is 7ns

Y AC

Solution Expanded
   
Y AC B C C
   
   
  ( )
Y AC B C C AC B C C
AC C A C C AC
   
   

Given the circuit below,
(a) Using a Truth Table and a K-map, minimize the logic
function
A
C
B
2ns
5ns
7ns
7ns Y

Def: Clock Period and Switching
Frequency
ClK
Tc = cycle period, seconds
0 Tc
Switching frequency,
1
c
f
T


D-FF Timing Parameters
Q
Q
SET
CLR
D
Qn+1
D
Pre
Rst
Clk
tsu thd
tq
Clk
D
q
Timing Diagram
0
Tsu= setup time
D must be stable (unchanging) tsu seconds before the clock edge
Thd = hold time
D must be stable thd seconds after the clock edge.
Tq = register delay time
Q becomes valid tq seconds after the clock edge.
time
If Tsu or Thd are violated, data are NOT stored in D-FF

Maximum Switching Frequency
How fast can our circuits operate

CLK
Reset
No delay on this net
CL
F
tcl
R
E
G
IN OUT
tin
Input Buffer Output Buffer
X Y
tout
tq
thd
tsu
Maximum Switching Frequency Model
W
We need to find the minimum time, Tc,min, needed
to propagate a signal from input X to node W.
No feedback and thd=0ns

CLK
Reset
CL
F
tcl
R
E
G
IN OUT
tin
X Y
tout
tq
thd
tsu
Maximum Switching Frequency Model
W
From the model, we see that the minimum cycle time is
,min
c in cl su
T t t t
  
Register Setup time
No feedback and thd=0ns

Timing Diagram
Maximum Switching Frequency
tin+tcl tsu tin+tcl tsu
ClK
W
Y tq+tout tq+tout
X Tc.min Tc.min
Tc,min
,min
c in cl su
T t t t
   max
,min
1
c
f
T

This model assumes tq+tout < tin+tcl+tsu

Setup Time Violation
tsu
tin+tcl tin+tcl
tin+tcl
0 Tc
Clock
Ideal Case
Clock too
Fast
tin+tld
tin+tld
tsu
tsu
We have a setup time violation because the clock is too fast!!!
Clock is too fast!!!

Correcting a Setup Time Violation
1. Slow down the clock so that
c in cl su
T t t t
  
However, in most cases, Tc is a system parameter which cannot
be changed. Plus, most users want their designs to go faster not
slower.
2. Use a pipeline design. Let’s examine this option more closely.

CLK
Reset
CL
F
tcl
R
E
G
IN OUT
tin
X Y
tout
tq
thd
tsu
Original Design
W
max,
1 1
,
original cl in su
in cl su cl
f for t t t
t t t t
  
 

CL
F1
tcl1
Y
tcl2
CL
F2
X
F Logic
Let’s break the F Logic into two components, so that
F = F1 + F2 and tcl = tcl1 + tcl2
Pipeline Design

CLK
Reset
IN OUT
tin
X Y
tout
R
E
G
tq
thd
tsu
CL
F1
tcl1
R
E
G
tq
thd
tsu
CL
F2
tcl2
Pipeline Design
Now, let’s add two register blocks. One between F1 and F2 and
another one at the output.

CLK
Reset
IN OUT
tin
X Y
tout
R
E
G
tq
thd
tsu
CL
F1
tcl1
R
E
G
tq
thd
tsu
CL
F2
tcl2
Pipeline Design
Minimum Cycle Time for Each Stage
,1 ,1
c in cl su
T t t t
   ,2 ,2
c q cl su
T t t t
  
Stage 1 Stage 2
in q
Let t t

Stage 1 Stage 2
For simplicity,

CLK
Reset
IN OUT
tin
X Y
tout
R
E
G
tq
thd
tsu
CL
F1
tcl1
R
E
G
tq
thd
tsu
CL
F2
tcl2
Pipeline Design
Maximum Switching Frequency Calculation
Stage 1 Stage 2
 
,min ,1 ,2
max ,
c c c
T T T
 max
,min
1
c
f
T


Pipeline Design
,1 ,1
c q cl su
T t t t
   ,2 ,2
c q cl su
T t t t
  
 
,min ,1 ,2
max ,
c c c
T T T

where
,1 ,2
2
cl
cl cl
t
Let t t
 
,min ,
2 2 2
cl cl cl
c q su su q
t t t
T t t for t t
    
;
max, max,
,min
1 2
2
PL original
c cl
f f
T t
  
We have,
or,
so,

CLK
Reset
IN OUT
tin
X Y
tout
R
E
G
tq
thd
tsu
CL
F1
tcl1
R
E
G
tq
thd
tsu
CL
F2
tcl2
Pipeline Design
Stage 1 Stage 2
In other words, the pipeline design can run 2x as fast as the
original design. Let’s look at a timing diagram to see why.

Pipeline Design Timing Diagram
tq+tcl
0 Tc
Clock
tsu
tsu
2Tc
tq+tcl1 tsu
tq+tcl1
tsu
tsu
tq+tcl2 tq+tcl2
Original
Design
Stage1
Stage2
Stages 1
and 2 run
in parallel
Too Slow

Pipeline Design
Reg
tsu,t
hd,tq
CL
Tld,1
Out
tout
Stage 1
.....
Inp
tin
Reg
tsu,t
hd,tq
CL
Tld,2
Stage 2
Reg
tsu,t
hd,tq
CL
Tld,n-1
Stage n-1
Reg
tsu,t
hd,tq
CL
Tld,n
Stage n
Outputs
INPUTS
PIPE
Let’s extend this concept to an N stage pipe
What is the maximum switching frequency?
Let the total logic delay Tcl = Tcl1+Tcl2+ …. + Tcl,N

Pipeline Design
Reg
tsu,t
hd,tq
CL
Tcl,1
Out
tout
Stage 1
.....
Inp
tin
Reg
tsu,t
hd,tq
CL
Tcl,2
Stage 2
Reg
tsu,t
hd,tq
CL
Tcl,n-1
Stage n-1
Reg
tsu,t
hd,tq
CL
Tcl,n
Stage n
Outputs
INPUTS
PIPE
,
cl
q in cl n
T
Let t t and t
N
  i.e. all stages have equal delays.
We have for each stage: ,
cl
c n q su
T
T t t
N
  

Pipeline Design
Reg
tsu,t
hd,tq
CL
Tcl,1
Out
tout
Stage 1
.....
Inp
tin
Reg
tsu,t
hd,tq
CL
Tcl,2
Stage 2
Reg
tsu,t
hd,tq
CL
Tcl,n-1
Stage n-1
Reg
tsu,t
hd,tq
CL
Tcl,n
Stage n
Outputs
INPUTS
PIPE
Now, assume
cl
su q
T
t t
N
 
,min ,
cl cl
c c n q su
T T
T T t t
N N
    
So
max
,min
1
original
c cl
N
f Nf
T T
  
Or,

Pipeline Design
Reg
tsu,t
hd,tq
CL
Tcl,1
Out
tout
Stage 1
.....
Inp
tin
Reg
tsu,t
hd,tq
CL
Tcl,2
Stage 2
Reg
tsu,t
hd,tq
CL
Tcl,n-1
Stage n-1
Reg
tsu,t
hd,tq
CL
Tcl,n
Stage n
Outputs
INPUTS
PIPE
In other words, the pipelined design will operate N times faster than
the original design.
pipe original
f Nf


Pipeline Design
Reg
tsu,t
hd,tq
CL
Tcl,1
Out
tout
Stage 1
.....
Inp
tin
Reg
tsu,t
hd,tq
CL
Tcl,2
Stage 2
Reg
tsu,t
hd,tq
CL
Tcl,n-1
Stage n-1
Reg
tsu,t
hd,tq
CL
Tcl,n
Stage n
Outputs
INPUTS
PIPE
Now, let’s set N  
,min ,
cl
c c n q su q su
T
T T t t t t
N
     
So
0 0 0 0
0
,min
c q su
T t t
 
Or, constant

Pipeline Design
Reg
tsu,t
hd,tq
CL
Tcl,1
Out
tout
Stage 1
.....
Inp
tin
Reg
tsu,t
hd,tq
CL
Tcl,2
Stage 2
Reg
tsu,t
hd,tq
CL
Tcl,n-1
Stage n-1
Reg
tsu,t
hd,tq
CL
Tcl,n
Stage n
Outputs
INPUTS
PIPE
So,
max
,min
1 1
c q su
f
T t t
 

constant

Pipeline Design
Reg
tsu,t
hd,tq
CL
Tcl,1
Out
tout
Stage 1
.....
Inp
tin
Reg
tsu,t
hd,tq
CL
Tcl,2
Stage 2
Reg
tsu,t
hd,tq
CL
Tcl,n-1
Stage n-1
Reg
tsu,t
hd,tq
CL
Tcl,n
Stage n
Outputs
INPUTS
PIPE
In other words, the absolute maximum frequency of any design is fixed at
max
,min
1 1
c q su
f
T t t
 

We can use this formula to perform a “back of the envelope” calculation to
determine if a desired switching frequency is “feasible”

Pipeline Design- Tradeoffs
Reg
tsu,t
hd,tq
CL
Tcl,1
Out
tout
Stage 1
.....
Inp
tin
Reg
tsu,t
hd,tq
CL
Tcl,2
Stage 2
Reg
tsu,t
hd,tq
CL
Tcl,n-1
Stage n-1
Reg
tsu,t
hd,tq
CL
Tcl,n
Stage n
Outputs
INPUTS
PIPE
The pipeline approach is a very powerful design technique.
However, we have two major trade-offs using a
pipelined design. They are
1. Data Load Time and 2. Data Latency Time

Reg
tsu,t
hd,tq
CL
Tcl,1
Out
tout
Stage 1
.....
Inp
tin
Reg
tsu,t
hd,tq
CL
Tcl,2
Stage 2
Reg
tsu,t
hd,tq
CL
Tcl,n-1
Stage n-1
Reg
tsu,t
hd,tq
CL
Tcl,n
Stage n
Outputs
INPUTS
PIPE
DATA Load Time
At power-up, we must first “load” the pipeline. This will require a time of
 
,min
cl
load c q su q su cl
T
T NT N t t N t t T
N
 
      
 
 
N  
Note as,
load
T  
we find,
unacceptable

Reg
tsu,t
hd,tq
CL
Tcl,1
Out
tout
Stage 1
.....
Inp
tin
Reg
tsu,t
hd,tq
CL
Tcl,2
Stage 2
Reg
tsu,t
hd,tq
CL
Tcl,n-1
Stage n-1
Reg
tsu,t
hd,tq
CL
Tcl,n
Stage n
Outputs
INPUTS
PIPE
DATA Latency Time
Data will require a finite time to progress through the pipe, this is
equivalent to the Data load time.
 
,min
cl
latency c q su q su cl
T
T NT N t t N t t T
N
 
      
 
 
N  
Note as, latency
T  
we find,
unacceptable

07_Digital timing_&_Pipelining.ppt

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