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# Datapath subsystem multiplication

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THIS PPT IS PRESENTED TO PROF. RAVITESH MISHRA FROM EC FINAL YEAR STUDENTS MADE FROM RAZAVI,DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS ON DATAPATH SUBSYSTEM-MULTIPLICATION

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### Datapath subsystem multiplication

1. 1. DATAPATH SUBSYSTEMS : MULTIPLICATIONSUBMITTED BY : SUBMITTED TO:Saurav Shekhar (EC 94) Ravitesh MishraSwati Soni (EC 109) APVijeta Nair (EC 113) EC Dept.Sachin Rajak (EC 84)Roshan Singh (EC 80)Multiplication 04/04/2013 Slide 1
2. 2. CONTENT Introduction Data path Operators Multiplications Unsigned Array Multiplication 2’s Complement Array Multiplication Wallace Tree Multiplication Serial MultiplicationMULTIPLICATION Slide 2
3. 3. INTRODUCTION Data path elements include adders, multipliers, shifters, BFUs, etc. – The speed of these elements often dominates the overall system performance so optimization techniques are important. – However, as we will see, the task is non-trivial since there are multiple equivalent logic and circuit topologies to choose from, each with adv./ disadv. in terms of speed, power and area. – Also, optimizations focused at one design level, e.g., sizing transistors, leads to inferior designs.Datapath Slide 3
4. 4. DATA PATH OPERATORS It forms an important subclass of VLSI circuit. This arises because n-bit data generally processed, which naturally leads to the ability to use n identical circuits to implement the function. Also, data operations may be sequenced in time or space to each other. Data may be arranged to flow in one direction why any control signals are introduced in an orthogonal direction to the dataflow. Common Data Path Operators are: Adders, One/Zero Detectors, Comparators, Counters, Boolean Logic Units, Error-Correcting Code Blocks, Shifters, MULTIPLIERS and DividersDatapath Slide 4
5. 5. MULTIPLICATION Multiplication is a less common operation than addition but is still essential for microprocessors, digital signal processors and graphics engines. Multiplications algorithm is used to illustrate methods of designing different cells so that they fit into larger structures. The most common form of multiplication consists of forming the product of two unsigned (positive) binary numbers. This can be achieved through the traditional technique taught in primary school, simplified to base 2. For Example, the multiplication of two positive 4-bit binary integers 12 to base 10 and 5 to base 10 is given below:-Multiplication Slide 5
6. 6. MULTIPLICATION Example: 1100 : 12 10 0101 : 5 10 1100Multiplication Slide 6
7. 7. MULTIPLICATION Example: 1100 : 12 10 0101 : 5 10 1100 0000Multiplication Slide 7
8. 8. MULTIPLICATION Example: 1100 : 12 10 0101 : 5 10 1100 0000 1100Multiplication Slide 8
9. 9. MULTIPLICATION Example: 1100 : 12 10 0101 : 5 10 1100 0000 1100 0000Multiplication Slide 9
10. 10. MULTIPLICATION Example: 1100 : 12 10 0101 : 5 10 1100 0000 1100 0000 00111100 : 60 10Multiplication Slide 10
11. 11. MULTIPLICATION Example: 1100 : 12 10 multiplicand 0101 : 5 10 multiplier 1100 0000 partial 1100 products 0000 00111100 : 60 10 product M x N-bit multiplication – Produce N M-bit partial products. – Sum these to produce M+N-bit products.Multiplication Slide 11
12. 12. DOT DIAGRAM Each Dot Represents A BitMultiplication Slide 12
13. 13. UNSIGNED ARRAY MULTIPLIER To multiply two 4-bit unsigned array number A3 A2 A1 A0 and B3 B2 B1 B0 The basic block of array is Full Adder Block (FA) and total number of FA block is required is 4 X 3 = 12. The Full Adder block generates output as :- SUM = Α ⊕ Β ⊕ CΙ CO = Α .Β + Β .CΙ + CΙ . AArray Multiplier Slide 13
14. 14. In general for an n-bit unsigned array multiplier the number offull adder required is nx(n-1). Each AiBj realized using “AND”gate. Each output bit is computed by adding the appropriateAiBjin the respective column and carries from previous column.To get the final 8-bit output P7 P6 . . . P2 P1 P0 we have to wait forthe maximum combinatorial delay of sum generation of two FAblocks (row of A3B0) plus carry propagation time of 4 FAblocks of last and last but one column. Thus it is a fastmultiplier but hardware complexity is also high.Array Multiplier Slide 14
15. 15. GENERAL FORM Multiplicand: Y = (yM-1, yM-2, …, y1, y0) Multiplier: X = (xN-1, xN-2, …, x1, x0) Product:  M −1 j   N −1 i  N −1 M −1 P =  ∑ y j 2 ÷ ∑ xi 2 ÷ = ∑ ∑ xi y j 2 i+ j  j= 0   i= 0  i= 0 j= 0Multiplication Slide 15
16. 16. PARTIAL PRODUCTSMultiplication Slide 16
17. 17. ARRAY MULTIPLIERArray Multiplication Slide 17
18. 18. 2’s COMPLEMENT ARRAY MULTIPLICATIONMultiplication of 2’s complement numbers are seem moredifficult because some partial products are negative and mustbe subtracted. We know that the most significant bit of a 2’scomplement number has a negative weight. Hence, the productis given by :-2’s COMPLEMENTARRAY MULTIPLICATION Slide 18
19. 19. The equation shows that, two of the partial products havenegative weight, hence should be subtracted rather than added.The Baugh-Wooley multiplier algorithm handles subtraction bytaking the 2’s Complement of terms to be subtracted (i.e.inverting the bits and adding 1). The figure in the next slideshows the partial product that must be summed. The upperparallelogram represents the unsigned multiplication of all butthe most significant bits of the inputs. The next roe is single bitcorresponding to the product of the most significant bits. Thenext two pairs of rows are the inversions of the term tosubtracted. Each term has implicit leading and trailing 0’s –which are inverted to leading and trailing 1’s. Extra 1’s must beadded in the least significant column when taking the 2’scomplement.2’s COMPLEMENTARRAY MULTIPLICATION Slide 19
20. 20. 2’s COMPLEMENTARRAY MULTIPLICATION Slide 20
21. 21. The multiplier delay depends on the number of partialproducts rows to be summed. The modified Baugh-Wooleymultiplier reduces this number of partial products by precomputing the sums of constant 1’s and pushing some of theterms upwards into extra columns. The figure in next slideshows such arrangement.2’s COMPLEMENTARRAY MULTIPLICATION Slide 21
22. 22. 2’s COMPLEMENTARRAY MULTIPLICATION Slide 22
23. 23. 2’s COMPLEMENTARRAY MULTIPLICATION Slide 23
24. 24. 2’s COMPLEMENT GENERATOR2’s COMPLEMENTARRAY MULTIPLICATION Slide 24
25. 25. WALLACE TREE MULTIPLICATION A Carry Save Adder (CSA) is effectively a 1’s counter that adds the number of 1’s on the input and encodes them on the sum carry outputs. Therefore a CSA is also known as a (3,2) counter, because it converts three input into a count encoded in two outputs. The carry out is passed to the next most significant column. And this process is go on and on. The output is produced in carry-save redundant form suitable for the final CPA. WALLACE TREE MULTIPLICATION Slide 25
26. 26. An Adder as a 1’s Counter A B C CARRY SUM Number of 1’s 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 0 2 1 0 0 0 1 1 1 0 1 1 0 2 1 1 0 1 0 2 1 1 1 1 1 3WALLACE TREE MULTIPLICATION Slide 26
27. 27. WALLACE TREE MULTIPLICATION Slide 27
28. 28.  The column addition is slow because only one CSA is active at a time. Another way to speed the column addition is to sum partial products in parallel rather than sequentially. The figure in the next slide shows a Wallace Tree using this approach. The Wallace Tree requires :- N  log3/2   2  levels of (3,2) counters to reduce N input down to 2 carry-save redundant from outputs.WALLACE TREE MULTIPLICATION Slide 28
29. 29. WALLACE TREE MULTIPLICATION Slide 29
30. 30. SERIAL MULTIPLICATION A serial multiplier multiplies 2 input numbers in synchronism with clock. One method of serial multiplication is by repeated addition. Multiplication of two binary numbers A and B is done by repeated addition of B+B+B+…..+B upto A times. Implementation of serial multiplier by repeated addition to multiply two 4-bit unsigned binary number A3 A2 A1 A0 and B3 B2 B1 B0 .Serial Multiplication Slide 30
31. 31. The basic building blocks used are :-1) ADDER (ADD8) to add two 8-bit numbers.2) 4-bit Binary Up Counter.1) COMPARATOR (COM4) which compares two 4-bit binary numbers and output is high if two numbers are same.2) Data Register (FD8CE) which consists 8 D Flip-Flop to store 8-bit data.Serial Multiplication Slide 31
32. 32. The 8-bit data structure is used for internal arithmetic and itavoids the chances of overflow. Zero Padding is done inupper 4-bits of B and 8-bit input is fed one input of adderblock. The output of the Adder is fed to the input of the DateRegister. The output of Data Register is fed to the other inputof the adder block. The Date Register and Counter used havea Clock Enable (CE) and Asynchronous Clear Input (CLR).Serial Multiplication Slide 32
33. 33. Serial Multiplication Slide 33
34. 34. ADVANTAGES Array multipliers may be pipelined to decrease clock period at the expense of latency. Partial product generation and accumulation are merged, which makes calculation easy.Multiplication Slide 34
35. 35. THANK YOUMultiplication Slide 35
36. 36. Multiplication Slide 36