Abdelrahman Abdallah Abdelfatah Elskhawy is seeking a challenging opportunity in digital design and embedded systems. He has a BSc in electronics and communication from Cairo University, graduating with very good grades. His graduation project involved designing a 64-bit floating point adder/subtractor using Verilog. He has experience as an embedded systems developer and has skills in Verilog, VHDL, C programming, and CAD tools like Cadence and Quartus. In his free time he enjoys martial arts, chess, and reading.

1. Abdelrahman Abdallah Abdelfatah Elskhawy
41 Elkawmeya Elarabiya street, Mashaal, El- Haram,
Giza, Egypt
elskhawy.a@gmail.com
(+2) 0109-28-60-220
Military status: Exempted
OBJECTIVE A challenging opportunity in the

2. eld of Digital Design , embedded systems to build
upon and utilize my academic background, besides improving communication and
leadership skills.
EDUCATION 2008{2013 BSc: Cairo University, Cairo, Egypt.
Department of Electronics and Communication, Faculty of Engineering.
Elective Modules: Analog & Digital VLSI, and Industrial Electronics.
Cumulative grade: very good (79 %).
Graduation Project: Design of 64-bit IEEE standard Modal Interval binary Float-
ing point Adder/Subtractor with Decorations using Verilog.
The design targeted Stratix III FPGA family, and 65nm TSMC ASIC tech-
nology. Synthesis were done using Altera Quartus-II, and Synopses Design
Compiler respectively.
Noteworthy this is the 2nd hardware implementation of this unit and the 1st
implementation with the Decorations feature complying with the draft stan-
dard IEEE-P1788.
Presented at SCAN 2014 conference, University of Wurzburg, Germany in
September 2014, and will be published in Springers LNCS.
Winner of the 1st place inTarek Gamal El Din annual competition for grad-
uation projects in EECE dept., Faculty of Engineering, Cairo University.
Supervised by Prof. DR/ Hossam A.H. Fahmy, member of IEEE P1788 work-
ing group. Graded with Excellent.
Projects 18 Instruction simple Microprocessor using VHDL.
Design and layout of 8-bit ripple-carry adder chip.
Remote Terminal Unit (enrolled in EEDs projects).
Data acquisition system using
ash memory and PIC microcontroller.
MCQ grading system using a microcontroller, PC serial interface, and a Java code.
Technical skills
Knowledge
Maintaining very good knowledge for Digital, Analog, and MEMS design con-
cepts, layouts, and problems.
Very good command of using Cadence, Modelsim, Quartus, Synopses Design
Compiler, Pspice, Dip trace, ARES, L-Edit, and Proteus.
Very good experience in FPGA/ASIC design
ow.
Experienced in Verilog, and VHDL RTL design, simulation, synthesis, analysis,
and low power design.
Good knowledge of embedded C-programming, Microcontroller architecture,
and real time design.