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ARVIND_BALAKUMAR_Resume
- 1. ARVIND BALAKUMAR 1337 West24th street, Los Angeles, California-90007 Mobile: +1 (213)-327-4496 Email: balakuma@usc.edu OBJECTIVE: To obtain a summer Internship in a simulating and challenging milieu, that enables maximum utilization of my skills and expertise in order to make a positive difference in the organization EDUCATION: University of Southern California (USC), Los Angeles, California August 2014-May 2016 Viterbi School of Engineering Master of Science, Electrical Engineering CGPA: 4.0/4.0 Sri Venkateswara College of Engineering, Tamil Nadu, India August 2010-May 2014 Bachelors of Engineering, Electronics and Communication CGPA: 8.67/10 TECHNICAL SKILLS: Ø Tools : Cadence-Virtuoso, Cadence-Allegro Design Entry Capture, Xilinx ISE, ModelSim, LTpice, Matlab, Xcode Ø Programming Languages: C, C++, Objective-C, SQL Ø Scripting Languages : Perl, Bash Ø Operating systems : MacOSX, Windows COURSES: Ø Fall 2014 : EE457-Computer Systems Organization, EE477L –MOS VLSI Circuit Design, EE590- Directed Research Ø Spring 2015: EE533- Network Processor Design and Programming, EE577A- VLSI System Design INTERNSHIPS: • Larsen & Toubro, Technology services: December 2013-May 2014 - Developed a Universal Wireless Mobile Charger based on the Qi (“Chee”) wireless power standard. - Designed the complete schematics in Cadence Allegro Design Entry Capture following the specifications provided by the company. - Completed the entire board bring up in the given time and carried out required test cases to ensure proper functionality. PROJECTS: • Design of a Multi Core Network Processor on NetFPGA: Spring 2015 - Designed a 5 stage Pipelined data path using Xilinx ISE, in Verilog. Emulated it on Vertex 2 Pro NetFPGA. - Designed a custom ISA for the Network processor, which supports 30 instructions. - Built a compiler using Perl that converts MIPS assembly code to our custom machine language that can directly be fed into the Instruction Memory of the processor. • Network Intrusion Detection (IDS) Engine: Spring 2015 - Designed a Network Intrusion Detection engine partially in Schematics and partially in Verilog using Xilinx ISE. - The engine detects malicious Network packets and drops them without forwarding to the next node. - The engine can detect up to 20 malicious packets of 7 Bytes wide each, which can be programmed during run time. • Single Core Processor – VLSI System Design: Spring 2015 - Designed a single core processor at gate level using Cadence Virtuoso. Improved performance of the processor by adding Forwarding and Hazard detection units. - Built a 512 bit SRAM with single read and write port, that was used as the Memory in the processor. - Reduced the combinational logic path delay by sizing the gates using Logical effort. Also optimized the power consumption of critical cells using Power gating. • Design of a Neuron cell - MOS VLSI Circuit Design: Fall 2014 - Implemented a neuron cell that provides a firing pulse based on the input stimuli. - Learned key layout strategies and techniques to make circuits small and fast. RESEARCH AND PUBLICATIONS: • Directed Research: Wireless power distribution to sensor clusters using electromagnetic induction under Professor Dr.Edmond A.Jonckheere, University of Southern California. • “Pixel detection and elimination algorithm to control traffic congestion aided by Fuzzy logic”- Fifth International Conference on Advanced Computing, ICoAC 2013 (IEEE Madras section), ISBN: 978-1-4799-3447-8. RESPONSIBILITIES AND POSITIONS: • Secretary of Electronics and Communication Association in College and organized a National Level Symposium “PANORAMA”. • Served as an external guide for school students at M.K.M Matriculation school, for an electronics project “Laser in Communication”.