This document discusses the design and simulation of a Wi-Fi data link layer transmit frame controller. It aims to understand WiMAX MAC layer specifications, architecturally design components based on those specifications, and behaviorally model and test the design blocks through stimulus modules. Specifically, it involves generating MAC frames for data, control, and management and adding header error control and payload cyclic redundancy check values. A FIFO data buffer interface and serializer are used to transmit the frames from the MAC layer.

1. DESIGN AND SIMULATION OF WI-FI DATA LINK LAYER
TRANSMIT FRAME CONTROLLER
ABSTRACTS
The main problem with Broad band access is that it is pretty expensive and it doesn’t reach
all areas. The main problem with WI-FI access is that hot spots are very small, so coverage is
sparse.
The WI-MAX technology that solved all these problems would provide high speed of
broad band service, much easier to extend and broad coverage area like cell phone network
instead of small WI-FI hotspots. In practical terms WI_MAX would operate similar to WI-FI.
Objective of this Project Understands of the Wi-MAX MAC Layer Specifications,
Architectural Design from specifications, Behavioral modeling of Design blocks, Design of
stimulus modules to test the functionality of Design Blocks, Synthesize design to extract Gate
level list.
The IEEE 802.16 standard for broadband wireless access was recently approved. It
defines a physical layer for systems operating at frequency bands between 10 and 66 GHz, a
medium access control (MAC) Protocol and the convergence layers for carrying protocols
such as IP, ATM and Ethernet. An IEEE 802.16 system consists of a base station and one
more or more subscriber stations. The protocol defines a physical layer, Medium Access
Control (MAC) layer and service specific convergence sub layers for transport of IP, Ethernet
and ATM. Its primary responsibility is to provide a reliable mechanism for exchanging
transaction packets (Data, Control and Management) on the communication channel through
Physical layer (RF Layer).
This project includes the generation of various MAC Frames (Data, control and
management), of 16-bit HEC for header and 32-bit CRC pay load data, FIFO data buffer
interface for transmitter, serializing the data using byte to bit converter and MAC transmitter
SMC implementation. The overall System Architecture will be designed using HDL language
and simulation, synthesis and FPGA implementation (Translation, Mapping, Placing and
Routing) will be done using various FPGA based EDA Tools.