The document discusses design verification testing using logic simulation to assess system operations and verification quality. It contrasts compiled driven and event driven simulations, emphasizing aspects like timing considerations and initialization needs in sequential circuits. Additionally, it highlights the importance of fault simulation to improve test quality by determining undetected faults and covers topics such as fault coverage and various fault types in circuits.

1. Pg. No. 39 to 64
M.Abramovici, M.A. Breuer, A.D. Friedman, “Digital
systems testing and testable design”, Jaico Publishing
House.

2.  It is a form of design verification testing that
uses a model of the system.

3.  Logic simulation is used to verify operation of
the system is:
 Other applications of simulation in the design
process are:

4.  Simulation replaces prototypes with software
model with advantages as :

5.  Problems in Simulation Based Design
Verification

6.  Compiled driven simulation :
◦ It executes a complied code model
◦ Compiled code is generated by RTL or Functional
programming.
◦ It is mainly oriented towards functional verification
◦ It is not concerned with the timing of the circuit.
 Event Driven Simulation :
◦ Applicable to asynchronous circuits
◦ Consider timing verification as it is event based.
◦ Can process real time inputs.

8.  In Sequential circuit, initialization is required.
 To process the unknown initial state
simulation algorithm uses unknown logic
value ‘u’={0,1}

14. Also process
control events
such as :
• Display values of
certain signals
• Checks expected
values

15.  Every gate adds delay to the signal
propagating through it.


16.  Delay from changes in input to the output response to the
input change.

17.  The minimum duration in input change necessary for output
to switch the state is called input inertial delay (dI )
 The output inertial delay model specifies that the gate output
can not generate a pulse with duration less than dI.

18.  Static Hazards:
 Let Q=1, A changes from 0 to 1, B changes
from 1 to 0 in given circuit.
 For short interval
 A=B=1 causes
 Short pulse at Z as
 Momentarily reset
 the latch to ‘0’
 Causes Static Hazard

23. 23
 Fault simulation Problem:
Given
 A circuit
 A sequence of test vectors
 A fault model
Determine
 Fault coverage - fraction (or percentage) of modeled faults
detected by test vectors
 Set of undetected faults
 Motivation
 Determine test quality and in turn product quality
 Find undetected fault targets to improve tests

24. 24
Verified design
netlist
Verification
input stimuli
Fault simulator Test vectors
Modeled
fault list
Test
generator
Test
compactor
Fault
coverage
?
Remove
tested faults
Delete
vectors
Add vectors
Low
Adequate
Stop

25. 25
 Circuit model: mixed-level
 Mostly logic with some switch-level for high-impedance
(Z) and bidirectional signals
 High-level models (memory, etc.) with pin faults
 Signal states: logic
 Two (0, 1) or three (0, 1, X) states for purely Boolean logic
circuits
 Four states (0, 1, X, Z) for sequential MOS circuits
 Timing:
 Zero-delay for combinational and synchronous circuits
 Mostly unit-delay for circuits with feedback

26. 26
 Faults:
 Mostly single stuck-at faults
 Sometimes stuck-open, transition, and path-delay faults;
analog circuit fault simulators are not yet in common use
 Equivalence fault collapsing of single stuck-at faults
 Fault-dropping -- a fault once detected is dropped from
consideration as more vectors are simulated; fault-
dropping may be suppressed for diagnosis
 Fault sampling -- a random sample of faults is simulated
when the circuit is large