© 2020 Xilinx
Vitis and Vitis AI:
Application Acceleration from
Cloud to Edge
Vinod Kathail
Fellow and Chief Architect SW Tools
© 2020 Xilinx
Industry Trends
Heterogeneous
Compute
Cloud to Edge AI Proliferation
Key challenge:
Programming &
integration of accelerators
Key challenge:
Need for retargetability
Key challenge:
Efficient ML acceleration and
integration in the whole application
© 2020 Xilinx
Heterogeneous
Compute
Cloud to Edge AI Proliferation
© 2020 Xilinx
Vitis Unified
Software Platform
© 2020 Xilinx
From Hardware to Software Programmable
5
© 2020 Xilinx
Vitis: Unified Software Platform
© 2020 Xilinx
Anatomy of an Accelerated Application
7
AXI (or PCIe)
CPU
Host Application
Drivers
XRT
XRT/OpenCL API
FPGA
Accelerated Functions
DMA Engine
Global Memory
AXI Interfaces
User
Application
Code
Acceleration
Platform
© 2020 Xilinx
Platform-Based Development Approach
Development is performed in the context of a platform
• A pre-configured system containing I/O, status monitoring, and lifecycle management
Standardized interfaces allow for automated composition of user functionality
© 2020 Xilinx
Vitis: Comprehensive Development Tool Suite
9
Build
Run
System level
Simulation
ARM
Compiler
AIE
Compiler
Vitis HLSHost CPU
System Compile/Link
Xilinx Runtime Library (XRT)
Device/Card Device/CardDevice/Card
Analyze
Host
Application Libraries
Application
C/C++
Target
PlatformRTL
Debug & Performance
Analysis
© 2020 Xilinx
Kernel Drivers
User Space Library
Kernel Drivers
OCL XMA AI C++ Python
XOCL ZOCL
Ultrascale
PCI-e Device
MPSoC/ACAP
PCI-e Device
MPSoC/
ACAP Device
MB scheduler ARM Scheduler ARM Scheduler
˃ Platform- and OS-independent APIs for
Device management
Memory management and data transfers
Accelerator execution management
˃ OpenCL wrappers, media frameworks,
and domain-specific APIs built on top of
base APIs
˃ Open source and available on GitHub
Xilinx Runtime (XRT)
© 2020 Xilinx
Open Source, Standards Based Libraries
11
https://github.com/Xilinx/Vitis_Libraries
Vision & Image Finance Data Analytics &
Database
Data Compression Data Security
Math Linear Algebra Statistics DSP Data Management
Domain-Specific Libraries
Common Libraries
400+ functions across multiple libraries for performance-optimized out-of-the-box acceleration
Library
Docs
Tests
Examples
Bench-
marks
© 2020 Xilinx
Vitis Vision Libraries
12
© 2020 Xilinx
Deploy: Embedded, Single Server, Scale-out
© 2020 Xilinx
Vitis drivers & runtime (XRT)
Frameworks
Vitis AI
Development
Kit
Vitis AI
Models
DSA
AI Quantizer AI CompilerAI Optimizer AI Profiler
LSTM DPU MLP DPUCNN DPU
60+ pretrained, optimized
reference models
Performance
improvement up to 10-20x
Tensor based ISA for true
software programmability
DSA – Domain Specific Architecture
DPU – DNN Processing Unit
Vitis AI: Real Time AI Inference Acceleration
© 2020 Xilinx
ACAP
Server
CPU
PCI
Express
FPGA
AI Engine
CPU
Cores
Video Analytics
Management
Computer
Vision
Primary
Detector (AI)
Object
Tracker
Secondary
Classifiers (AI)
Video
Decode
AI Embedded in Apps, Rarely the Whole App
© 2020 Xilinx
Example: Whole Application Acceleration
>>
16
Input
Image
2-3 days to integrate and test using Vitis and Vitis+AI Libraries
0
100
200
300
Tiny Yolo v3 Resnet-50 GoogleNet
Frames/sec
Speedup over CPU
CPU FPGA
Implemented either in FPGA or CPU Always in FPGA
© 2020 Xilinx
Example: Defect Detection
Low Latency: End-to-end < 250ms
>>
17
© 2020 Xilinx
Shell
Hardware
Developers
Application
Software Developers
AI and Data Scientists
(iterations in minutes)
Embedded
Developers
Putting it All Together
© 2020 Xilinx
Summary
19
Unified Software Platform
 Cloud to edge, software and AI
 Comprehensive tools, runtime, libraries and models
Standards, Open Source
 Participating in open source
 Use of standard environments & APIs
© 2020 Xilinx
Additional Resources
Please visit the following sites for more information
Vitis Unified SW Platform
• https://www.xilinx.com/products/design-
tools/vitis.html
Vitis Libraries
• https://www.xilinx.com/products/design-
tools/vitis/vitis-libraries.html
• https://github.com/Xilinx/Vitis_Libraries/
Vitis AI
• https://www.xilinx.com/products/design-
tools/vitis/vitis-ai.html
Visit the Avnet-Xilinx booth to see the following demonstrations
in action:
• Face Detection, Pedestrian Detection, Pose Estimation,
Machine Learning and more
• Hardware families include the Zynq Ultrascale+ and Versal
AI Core
• Demonstration platforms include our SmartCamera+,
Ultra96, and UltraZed
• Xilinx and Avnet staff will be available to answer any
questions
2020 Embedded Vision Summit
• Vitis and Vitis AI: Application Acceleration from Cloud to
Edge
• September 17, 2020, 11:00-11:30AM PDT
20

“Vitis and Vitis AI: Application Acceleration from Cloud to Edge,” a Presentation from Xilinx

  • 1.
    © 2020 Xilinx Vitisand Vitis AI: Application Acceleration from Cloud to Edge Vinod Kathail Fellow and Chief Architect SW Tools
  • 2.
    © 2020 Xilinx IndustryTrends Heterogeneous Compute Cloud to Edge AI Proliferation Key challenge: Programming & integration of accelerators Key challenge: Need for retargetability Key challenge: Efficient ML acceleration and integration in the whole application
  • 3.
  • 4.
    © 2020 Xilinx VitisUnified Software Platform
  • 5.
    © 2020 Xilinx FromHardware to Software Programmable 5
  • 6.
    © 2020 Xilinx Vitis:Unified Software Platform
  • 7.
    © 2020 Xilinx Anatomyof an Accelerated Application 7 AXI (or PCIe) CPU Host Application Drivers XRT XRT/OpenCL API FPGA Accelerated Functions DMA Engine Global Memory AXI Interfaces User Application Code Acceleration Platform
  • 8.
    © 2020 Xilinx Platform-BasedDevelopment Approach Development is performed in the context of a platform • A pre-configured system containing I/O, status monitoring, and lifecycle management Standardized interfaces allow for automated composition of user functionality
  • 9.
    © 2020 Xilinx Vitis:Comprehensive Development Tool Suite 9 Build Run System level Simulation ARM Compiler AIE Compiler Vitis HLSHost CPU System Compile/Link Xilinx Runtime Library (XRT) Device/Card Device/CardDevice/Card Analyze Host Application Libraries Application C/C++ Target PlatformRTL Debug & Performance Analysis
  • 10.
    © 2020 Xilinx KernelDrivers User Space Library Kernel Drivers OCL XMA AI C++ Python XOCL ZOCL Ultrascale PCI-e Device MPSoC/ACAP PCI-e Device MPSoC/ ACAP Device MB scheduler ARM Scheduler ARM Scheduler ˃ Platform- and OS-independent APIs for Device management Memory management and data transfers Accelerator execution management ˃ OpenCL wrappers, media frameworks, and domain-specific APIs built on top of base APIs ˃ Open source and available on GitHub Xilinx Runtime (XRT)
  • 11.
    © 2020 Xilinx OpenSource, Standards Based Libraries 11 https://github.com/Xilinx/Vitis_Libraries Vision & Image Finance Data Analytics & Database Data Compression Data Security Math Linear Algebra Statistics DSP Data Management Domain-Specific Libraries Common Libraries 400+ functions across multiple libraries for performance-optimized out-of-the-box acceleration Library Docs Tests Examples Bench- marks
  • 12.
    © 2020 Xilinx VitisVision Libraries 12
  • 13.
    © 2020 Xilinx Deploy:Embedded, Single Server, Scale-out
  • 14.
    © 2020 Xilinx Vitisdrivers & runtime (XRT) Frameworks Vitis AI Development Kit Vitis AI Models DSA AI Quantizer AI CompilerAI Optimizer AI Profiler LSTM DPU MLP DPUCNN DPU 60+ pretrained, optimized reference models Performance improvement up to 10-20x Tensor based ISA for true software programmability DSA – Domain Specific Architecture DPU – DNN Processing Unit Vitis AI: Real Time AI Inference Acceleration
  • 15.
    © 2020 Xilinx ACAP Server CPU PCI Express FPGA AIEngine CPU Cores Video Analytics Management Computer Vision Primary Detector (AI) Object Tracker Secondary Classifiers (AI) Video Decode AI Embedded in Apps, Rarely the Whole App
  • 16.
    © 2020 Xilinx Example:Whole Application Acceleration >> 16 Input Image 2-3 days to integrate and test using Vitis and Vitis+AI Libraries 0 100 200 300 Tiny Yolo v3 Resnet-50 GoogleNet Frames/sec Speedup over CPU CPU FPGA Implemented either in FPGA or CPU Always in FPGA
  • 17.
    © 2020 Xilinx Example:Defect Detection Low Latency: End-to-end < 250ms >> 17
  • 18.
    © 2020 Xilinx Shell Hardware Developers Application SoftwareDevelopers AI and Data Scientists (iterations in minutes) Embedded Developers Putting it All Together
  • 19.
    © 2020 Xilinx Summary 19 UnifiedSoftware Platform  Cloud to edge, software and AI  Comprehensive tools, runtime, libraries and models Standards, Open Source  Participating in open source  Use of standard environments & APIs
  • 20.
    © 2020 Xilinx AdditionalResources Please visit the following sites for more information Vitis Unified SW Platform • https://www.xilinx.com/products/design- tools/vitis.html Vitis Libraries • https://www.xilinx.com/products/design- tools/vitis/vitis-libraries.html • https://github.com/Xilinx/Vitis_Libraries/ Vitis AI • https://www.xilinx.com/products/design- tools/vitis/vitis-ai.html Visit the Avnet-Xilinx booth to see the following demonstrations in action: • Face Detection, Pedestrian Detection, Pose Estimation, Machine Learning and more • Hardware families include the Zynq Ultrascale+ and Versal AI Core • Demonstration platforms include our SmartCamera+, Ultra96, and UltraZed • Xilinx and Avnet staff will be available to answer any questions 2020 Embedded Vision Summit • Vitis and Vitis AI: Application Acceleration from Cloud to Edge • September 17, 2020, 11:00-11:30AM PDT 20