This document discusses timing control in Verilog HDL. It describes three types of timing control: delay based, event based, and level sensitive. Delay based timing uses the # symbol to specify delays for procedural statements. Event based timing uses the @ symbol to trigger statements based on events. Level sensitive timing uses the wait statement. The document provides examples of implementing timing control for different cases.

1. 1
Verilog HDLVerilog HDL
ASIC DESIGN USING
FPGA
BEIT VII
KICSIT
Sept 17 2012 Lecture 9

2. 2
Timing Control
Sept 17 2012
• If there is no timing control, simulation time
does not advance.
• Simulated time can only progress by one of the
following:
• Gate or wire delay, if specified.
• A delay control, introduced by the # symbol.
• An event control, introduced by the @
symbol.
• The wait statement.
Lecture 9

3. 3
Timing Control
Sept 17 2012
• The Verilog language provides three types of
Timing Control.
• Delay based timing control
• Event based timing control
• Level sensitive timing control
Lecture 9

4. 4
Delay based Timing Control
Sept 17 2012
• Regular Delay Control (#)
• A non-zero delay with # is specified to the left
of a procedural assignment.
• specifies the time duration between initially
encountering the statement and when the
statement actually executes.
Lecture 9

5. 5
Delay based Timing Control
Sept 17 2012
• For example:
#10 A = A + 1 ;
specifies to delay 10 time units before
executing the procedural assignment statement.
• The # may be followed by an expression with
variables.
• For example:
#y x = x + 1 ;
Lecture 9

6. 6
Delay based Timing Control
Sept 17 2012 Lecture 9
• Regular Delay Control

7. 7
Delay based Timing Control
Sept 17 2012
• Intra-assignment Delay Control
• A non-zero delay with # is specified to the
right of a procedural assignment.
y = #10 x + z ;
Lecture 9

8. 8
Delay based Timing Control
Sept 17 2012
• Zero Delay Control
• Procedural statements in different always-initial
blocks may be evaluated at the same simulation
time.
• The order of execution of these statements in
different always-initial blocks is nondeterministic.
• Zero Delay Control is a method to ensure that a
statement is executed last, after all other
statements in that simulation time are executed
Lecture 9

9. 9
Delay based Timing Control
Sept 17 2012
• Zero Delay Control
• Zero Delay Control is used to eliminate race
conditions.
Lecture 9

10. 10
Event based Timing Control
Sept 17 2012
• An event is the change in the value on a register
or a net.
• can be utilized to trigger execution of a
statement or a block of statements.
Lecture 9

11. 11
Event based Timing Control
Sept 17 2012
• Events based timing control- (@)
Lecture 9

12. 12
Event based Timing Control
Sept 17 2012
• Example half adder implementation
Lecture 9

13. 13
Event based Timing Control
Sept 17 2012
• Example Behavioral edge-triggered DFF
Lecture 9

14. 14
Level based Timing Control
Sept 17 2012
• Level sensitive timing control wait (expr)
Lecture 9

15. 15
Conditional Statements
Sept 17 2012
• if and else
if (expr1)
true_stmt1 ;
else if (expr2)
true_stmt2 ;
else
def_stmt;
Lecture 9

16. 16
Multi-way Branching
Sept 17 2012
• Procedural Statement (case)
The keywords case, endcase and default are
used in the case statement.
case (expr)
item_1: stmt1;
item_2: stmt2;
..
default: def_stmt;
endcase Lecture 9

17. 17
Multi-way Branching
Sept 17 2012
• Example case
4-to-1 mux:
Lecture 9

18. 18
Multi-way Branching
Sept 17 2012
• There are two variations of the case
statement.
•casez treats all z values in the case
alternatives or the case expression as don’t
cares. All bit positions with z can also be
represented by ? in that position.
•casex treats all x and z values in the case
item or the case expression as don’t cares.
Lecture 9

19. 19
Multi-way Branching
Sept 17 2012
• casez Example:
Lecture 9

20. 20
Multi-way Branching
Sept 17 2012
• casex Example:
Lecture 9