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The HR Manager,
Dear Employer,
I am interested to apply for the position of PHYSICAL DESIGN ENGINEER.
I am enclosing my resume along with this cover letter that shows my well-built educational
background in the field of Physical Design. I have 1 year of VLSI industry experience in ASIC
Physical Design & done Advanced Diploma in ASIC Design at RV-VLSI Design Center,
Bangalore .The environment over there helped me a lot in improving my technical skills .I
feel that I can make significant contributions to your firm.
I would like to work with your organization. It would be a pleasure to Interview with you and
I am looking forward to hear from you soon.
• Expertise in Place & Route, Low Power design, STA, Logic Synthesis, Floor-planning,
CTS, Timing closure, DRC, SI issues
• Familiar with all aspects of ASIC integration including Floor planning,
Clock and Power distribution, global signal planning, I/O planning and hard IP
integration.
• Familiar with typical SoC issues such as multiple voltage and clock domains, ESD
strategies, mixed signal block integration, and package interactions.
• Familiar with Power budgeting, timing and physical convergence.
• Netlist to GDSII Implementation
o Floor plan, pin placement & special low power cell insertion , Place & Route,
Clock tree synthesis, Routing and optimization using Synopsys ICC and
SoC Encounter
o Static timing analysis using prime time and eco implementation in PNR tool.
o Signoff includes timing, DRC, ERC and LVS using Calibre and Quartz DRC.
• Good knowledge of TCL scripting.
• Resolving design and flow issues related to physical design.
• Physical & electrical verification, driving the signoff closure.
• Familiar with hierarchical design approach, top-down design.
Thank you for your time and consideration.
Sincerely,
USIRIKAYALA SAIDULU

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cover_letter

  • 1. The HR Manager, Dear Employer, I am interested to apply for the position of PHYSICAL DESIGN ENGINEER. I am enclosing my resume along with this cover letter that shows my well-built educational background in the field of Physical Design. I have 1 year of VLSI industry experience in ASIC Physical Design & done Advanced Diploma in ASIC Design at RV-VLSI Design Center, Bangalore .The environment over there helped me a lot in improving my technical skills .I feel that I can make significant contributions to your firm. I would like to work with your organization. It would be a pleasure to Interview with you and I am looking forward to hear from you soon. • Expertise in Place & Route, Low Power design, STA, Logic Synthesis, Floor-planning, CTS, Timing closure, DRC, SI issues • Familiar with all aspects of ASIC integration including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. • Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions. • Familiar with Power budgeting, timing and physical convergence. • Netlist to GDSII Implementation o Floor plan, pin placement & special low power cell insertion , Place & Route, Clock tree synthesis, Routing and optimization using Synopsys ICC and SoC Encounter o Static timing analysis using prime time and eco implementation in PNR tool. o Signoff includes timing, DRC, ERC and LVS using Calibre and Quartz DRC. • Good knowledge of TCL scripting. • Resolving design and flow issues related to physical design. • Physical & electrical verification, driving the signoff closure. • Familiar with hierarchical design approach, top-down design. Thank you for your time and consideration. Sincerely, USIRIKAYALA SAIDULU