Rohit Gangadharan is seeking a position in the semiconductor industry with an emphasis on VLSI design. He has over 2 years of experience as a design engineer working on 16nm processor and SerDes blocks. He has expertise with EDA tools like Cadence Encounter and Synopsys tools. For his MTech he worked on implementing a Leon processor in 45nm technology. Some of the challenges he has faced include handling congestion, timing violations, DRC issues and implementing timing closure. He is proficient in Verilog, Perl, and Linux.

1. ROHIT GANGADHARAN
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PROFILE To obtain a position in semiconductor industry which emphasizes growth, creativity, and
analytical thinking and to work in VLSI Domain where performance is rewarded with new
responsibilities and to grow along with the organization as a core member of the same.
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EDUCATIONAL QUALIFICATION
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WORK EXPERIENCE
2015(Oct) - Present Design Engineer at RealSilicon (Spontey Computer Systems) (1yr)
2015 Trainee Engineer in Orange Semiconductors Pvt.ltd (5 months)
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TECHNICAL SKILLS
ß Software Tools Mentor Graphics- Model Sim, Calibre (DRC LVC RVE DRV)
Cadence- Encounter (Innovus), Virtuoso, VOLTUS
Synopsis- Prime Time, DC, StarRC
ß Programming Languages Verilog HDL
ß Scripting Languages TCL, Perl, Shell
2013-2015 Master of Technology in VLSI Design
Amity University, Noida
First Class with 7.27 CGPA
2009-2013 Bachelor of Technology in ECE
RCET, Thrissur Calicut University
First Class with 7.14 CGPA
2007-2009 Senior Secondary (PCMB)
A.S.N Sr. Sec School, Delhi
Distinction with 81%
1997-2007 Secondary
K.E.S.S School, Delhi
Distinction with 85%
Contact:
+91-8150064264, +91-9911844264
Bangalore
Email : rohiquest@gmail.com
Skype: rohit.gangadharan2

2. ß Platform Worked on Windows XP/7 & Linux (Ubuntu, Redhat)
ß Acceptable knowledge in digital and CMOS fundamentals
ß Good grasping capabilities for new technology
ß Good understanding of synthesis, Physical Design flow, IR drop analysis, STA, fabrication
process, ECO, DFM
ß Sound written and oral communication skills
ß Worked on PNR flow: floorplanning, CTS, Routing, NDR rules, MMMC, ECO, Physical
verification, STA, power analysis
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PROJECTS
Project:
Project name: Cayenne
Organization: RealSilicon
Role: Design Engineer
Duration: 1 yr
ß Worked on 16nm technology to design a processor booster working on 10 Ghz.
ß Worked on PNR for hmc (1200x7500) with serdes working at 16 Ghz, noc, pcie (7500x1500), axi
(950x1800), fifo (450x450), adder blocks (64 bit 150x45) in cadence encounter tool.
ß Optimized skew by creation of regions and fences based on timing critical groups.
ß Created manual clock tree for some critical clocks in the design.
ß Worked on physical verification (drc’s and lvs) using caliber for the above blocks.
ß Worked on BUMP creation and assignment for cayenne blocks (hmc).
ß Worked on voltus to check the strength of power grid structure using DECAP decrement method.
ß Worked on STA for the above mentioned blocks using prime time and fixing by eco’s.
ß Worked on creating level shifter power grid structure for HMC block.
ß Have run and verified LEC on post layout netlist.
MTECH (Major Project)
Project 2 name: Block level implementation of Leon Processor
Organization: Orange semiconductors Pvt.ltd
Role: Physical Design Trainee
Technology information:
Technology used 45nm technology
No. of clocks 2
No. of instances 35000
No. of macros 4
No. of metal layers 9

3. Challenges faced: The whole PD flow was done till antenna (dangling wire) removal. The
variouschallenges faced are congestion, timing violations and DRV’s, connectivity violations.
The project also involved writing a Tcl script to add a buffer to the middle of a net to reduce hold
violations.
Tool used: Cadence encounter tool (Cadence® Encounter® Digital Implementation (EDI) System).
Project 1 name: Chip level implementation of DTMF chip.
Organization: Orange semiconductors Pvt.ltd
Role: Physical Design Trainee
Technology information:
Technology used 180nm technology
No. of clocks 2
No. of instances 9540
No. of macros 4
No. of metal layers 6
Challenges faced: The design actually worked at 14ns, which was constrained to 2ns and the
wholePD flow was done till antenna (dangling wire) removal. The various challenges faced are
high congestion, timing violations and DRV’s, connectivity violations.
Tool used: Cadence encounter tool (Cadence® Encounter® Digital Implementation (EDI) System)
MTECH (Minor Project)
Project name: Design, modeling and simulation of “Silicon Photonic Crystal Modulator”.
Duration: 6 weeks.
Summary: To design model and simulate a silicon photonic crystal modulator using a multi-
physicstool “COMSOL”. The electron and hole concentration, electric potential, electric field
variation of the modulator is noticed by varying the various parameters like materials, RI.
BTECH Project
Project name: Mains Monitor
Duration: 6 Weeks
Summary: To build a circuit on bread board to monitor the electrical circuit of an industry or
fordomestic purpose. A predefined voltage range is set and any voltage below or above that

4. range blows an alarm for a while and an inverter circuit provides the optimal voltage range
required. Later the circuit was even implemented in my college.
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TRAINING & CERTIFICATION
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Undergone training from Orange Semiconductors ltd as a Physical Design trainee.
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Completed training from HCL ltd. Noida in May 2013
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Completed training from Hykon Power Electronics ltd. in February 2012.
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Completed training from KELTRON electro ceramics ltd. in February 2012.
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PERSONAL DETAILS
Date of Birth 30
th
May, 1992
Current address Hennur cross, Kalyan Nagar 560043
Languages Hindi English Malayalam Tamil French
Fluent Fluent Native Intermediate Beginner
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REFERENCE
K. SRINIVAS
Sr. Manager
ksrao@wavesemi.com
Skype ID: skukutla
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I do hereby declare that all the particulars made above are true to the best of my knowledge and belief.
Place:Bangalore (ROHIT GANGADHARAN)
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