TRAP
INTERRUPT
• The interrupt I/O is a process of data transfer
where an external device can get the
attention of the microprocessor.
– The process starts from the I/O device
– The process is asynchronous.
TYPES OF INTERRUPTS
•
•
•
•

Maskable interrupts
Non-maskable interrupts
Vectored interrupts
Non-vectored interrupts
VECTORED INTERRUPTS
There are 5 interrupt inputs .They are
• INTR
• RST 5.5
• RST 6.5
• RST 7.5
• TRAP
MASKABLE INTERRUPTS:
• RST 5.5
• RST 6.5
• RST 7.5
NON-MASKABLE INTERRUPTS:
• TRAP
• These interrupts call locations are
Interrupts
Call location
1. TRAP
0024H
2. RST 7.5
003CH
3. RST 6.5
0034H
4. RST 5.5
002CH
TRAP
• This interrupt is a non-maskable interrupt. It is unaffected
by any mask or interrupt enable.
• TRAP bas the highest priority and vectored interrupt.
• TRAP interrupt is edge and level triggered. This means
hat the TRAP must go high and remain high until it is
acknowledged.
• In sudden power failure, it executes a ISR and send the
data from main memory to backup memory.
• The signal, which overrides the TRAP, is HOLD signal.
(i.e., If the processor receives HOLD and TRAP at the
same time then HOLD is recognized first and then TRAP
is recognized).
There are two ways to clear TRAP interrupt.
1. By resetting microprocessor (External
signal)
2. By giving a high TRAP ACKNOWLEDGE
(Internal signal)
Trap

Trap

  • 1.
  • 2.
    INTERRUPT • The interruptI/O is a process of data transfer where an external device can get the attention of the microprocessor. – The process starts from the I/O device – The process is asynchronous.
  • 3.
    TYPES OF INTERRUPTS • • • • Maskableinterrupts Non-maskable interrupts Vectored interrupts Non-vectored interrupts
  • 4.
    VECTORED INTERRUPTS There are5 interrupt inputs .They are • INTR • RST 5.5 • RST 6.5 • RST 7.5 • TRAP
  • 5.
    MASKABLE INTERRUPTS: • RST5.5 • RST 6.5 • RST 7.5 NON-MASKABLE INTERRUPTS: • TRAP
  • 6.
    • These interruptscall locations are Interrupts Call location 1. TRAP 0024H 2. RST 7.5 003CH 3. RST 6.5 0034H 4. RST 5.5 002CH
  • 7.
    TRAP • This interruptis a non-maskable interrupt. It is unaffected by any mask or interrupt enable. • TRAP bas the highest priority and vectored interrupt. • TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged. • In sudden power failure, it executes a ISR and send the data from main memory to backup memory. • The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
  • 8.
    There are twoways to clear TRAP interrupt. 1. By resetting microprocessor (External signal) 2. By giving a high TRAP ACKNOWLEDGE (Internal signal)